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Recent content by falloutmx

  1. F

    serial communication in FPGA

    what is your top module when implement? uart_tb.vhd is only used for simulation.
  2. F

    serial communication in FPGA

    as serial port is a low-speed port,we don't need anything to store it.it seems you should learning about baudrate and uart.
  3. F

    help regarding ethernet with microblaze

    you should learning emaclite's API and read the example.then try to init your ethernet. those things can be found in EDK directory
  4. F

    Can somebody explain thse XST warnings/info

    neg_check=int_ram[address_next]-int_ram[address_r] i think he want to read two data in one clock,fifo or dpram can't do this.
  5. F

    what's wrong with this program

    check your code again. as you didn't declare 'clock',there has many more error.
  6. F

    help in reading a large text file using verilog....

    why don't you use bram instead of reg
  7. F

    VHDL Problem in reading file HELP please

    plz minimize your design and check. if it works well, you should check your code. if not,that is the file's problem
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