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Recent content by ezbentley

  1. ezbentley

    How to simulate a netlist with other schematics in cadence

    Re: How to simulate a netlist with other schematics in caden Yeah, but that is kind of tedious. Is it possible to do it in the graphical interface(Analog Design Environment)?
  2. ezbentley

    How to simulate a netlist with other schematics in cadence

    I have a test bench in cadence that contains multiple schematics. I want to include a block, whose sub-circuit is represented by a spectre netlist, in the simulation. Basically I am trying to associate a symbol with a netlist instead of a schematic. Can anyone help me with a detail...
  3. ezbentley

    How does spectre handle noise from s-parameter nport device?

    spectre nport I am running noise simulation and it indicates that some of the major noise contribution comes from various s-parameter models in my circuit. How does spectre calculate the noise of those models? Technically s-parameter model does not contain any information about noise.
  4. ezbentley

    How does spectre handle noise from s-parameter nport device?

    I am running noise simulation and it indicates that some of the major noise contribution comes from various s-parameter models in my circuit. How does spectre calculate the noise of those models? Technically s-parameter model does not contain any information about noise.
  5. ezbentley

    spectrum analyzer and noise figure

    How about 1/f noise corner measurement? I tried to use Agilent PSA to do noise measurement. The problem is that it seems to have an internal LPF that actually cuts off the 1/f noise starting roughly below 10kHz. I think the PSA frequency range is from 3Hz to 26GHz. Is there an option to...
  6. ezbentley

    Differences between SSB, DSB, and IQ mixing

    ssb dsb Can someone explain to me the differences between "single sideband mixing," "double sideband mixing," and "IQ mixing?" Those are the terms I hear from work but don't really know what each one refers to specifically. Thanks
  7. ezbentley

    How to supress LO second harmonic in Gilbert cell mixer?

    I am designing a low voltage(1.8V) Gilbert cell mixer, which includes(from bottom to top) tail current mos, RF input mos, LO switching mos, and resistive load. Since LO has large amplitude, there would be a large common-mode second harmonic of LO at the drain of RF input mos, which may cause the...
  8. ezbentley

    Input bias of transconductor

    Since a gm cell works in an open loop fashion, how is the input bias determined? Should the gm cell include an internal biasing circuit to set the input point voltage? However, from some gm-c filter diagrams, it doesn't seem like there is internal bias, because some applications ground one of...
  9. ezbentley

    Input bias of transconductor

    Since a gm cell works in an open loop fashion, how is the input bias determined? Should the gm cell include an internal biasing circuit to set the input point voltage? However, from some gm-c filter diagrams, it doesn't seem like there is internal bias, because some applications ground one of...
  10. ezbentley

    Transconductor frequency limitation on gm-c filter?

    If a gm cell works in open loop, then how is the bias of the input determined? From the way the gm cells are used in gm-c filters, it doesn't seem like the gm cells are internally bias.
  11. ezbentley

    PSS doesn't converge with nport component

    Thanks a lot Mazz for pointing me to the right direction! The time domain delay on the spec sheet is about 1.2us, and TRAN simulation confirms this behavior. However, even though PSS converges after 3us, the voltage amplitude from PSS still differs from the measurement from TRAN. I am...
  12. ezbentley

    Transconductor frequency limitation on gm-c filter?

    Tolerance is not a major issue. My boss wants me to "try" to design one and see if it's any useful. No one at my work knows much about active filter. @@
  13. ezbentley

    PSS doesn't converge with nport component

    Mazz, Thanks for your advice. Let me clarify something. AC sim shows voltage loss of 20dB, which agrees with the spec. If I apply a sine wave in the passband, the output of the saw would show a sine wave of the same frequency with 60dB loss in TRAN simulation. The weird thing is, the output...
  14. ezbentley

    What is the minimum LNA noise figure achievable in CMOS 0.18

    Re: CMOS LNA obovolo: I love TSMC too, cuz I am from Taiwan too!

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