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Re: axi interconnect ip
You can download a free generic AXI master core from OpenCores.org
It has a configurable number of masters and slaves and such parameters.
Generic AXI interconnect fabric :: Overview :: OpenCores
An easy way to debug this is to change the memory array to be 8 bit (reg [7:0] mem;)
Write only once to address 0 and then you can see the memory being written / read in any simple waveform viewer.
What you really need is to start working!
Academic studies are fine but they're not actual work experience.
Since you will be looking for a job as a 'graduate' you shouldn't be worried about "remembering" stuff,
you should be focused on showing you are serious, hard-working, ready-to-learn kind...
I know this is not really what you asked but if it might be of any help...
I'm attaching a link to a Verilog generic FIR (hope it helps)
Generic FIR filter :: Overview :: OpenCores
GCD is trivial:
int GCD(int a, int b)
{
while( 1 )
{
a = a % b;
if( a == 0 )
return b;
b = b % a;
if( b == 0 )
return a;
}
}
Your problem is the C++ does mathematical calculations on 32 or 64 bit data.
What you need is a large number library to support...
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