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Recent content by evesjh77

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    Could anyone explain about Sensitivity in SSTA

    Hi. Now I'm studying SSTA and I have question about that. In the SSTA, Delay is : Delay = Delay(nominal) + a1 + a2 + a3 ... I can understand Delay(nominal). But I can't understand "a1,a2,a3.." that called "sensitivity". Could anyone explain about that detailedly? Thank you.
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    What is incremental delay on "instance arc"?

    Hi. Now I am doing pnr some asic chip by using cadence tool(Innovus). It is 10nm process and using AOCV. Anyway, my question is.. After Routing stage, incremental delay(delta delay) is appeared both net and cell. I know that incr delay is made by crosstalk. So I thought that it is added to...
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    [SOLVED] ICCOMPILER : Problem with locking

    Hi. I have same problem above that! and I know it is related to my workstation. But.. I can't solve it because I can not figure out which point is wrong... Please let me know how did you solve it. Thank you.
  4. E

    Install IC Compiler on CentOS6.1

    Hello I have installed the latest version of IC Compiler on CentOS 6.1 When I invoke icc_shell , the tool is invoked well. but when I start GUI Mode , IC Compiler is turned off ( There is a message "Exit IC Compiler") I have to install it on CentOS 6.1 . So .. could anybody tell me about this...
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    Can anybody tell me about single tri-state driver

    There are warning message about single tri-state driver when I invoke check_design in IC Compiler. I found about single tri-state driver, but I couldn't understand. Please anybody tell me about that.
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    Meanning of ideal nets

    Thanks rca!!! I perfectly understand about ideal net.
  7. E

    Meanning of ideal nets

    In IC Compiler, there is a command all_ideal_nets. But I don't know what it is.... I think it is net that is not routed. But that command is executed pre Route stage. Please tell me about that..
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    Could anybody tell me about Virtual Clock??

    Thank you Very Much. I'm exactly understand about Virtual Clock. Thank you so much.
  9. E

    Low power design using SoC encounter

    Hi. CPF is Common Power Format. It contains power domain , power logic ( Level Shifter , Isolation Cell, State retention Cell, Switch Cell and Control Signals ) , Power Mode and Technology information about Power logic. We can create power domain by using this command " create_power_domain -name...
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    Could anybody tell me about Virtual Clock??

    Please tell me about "Virtual Clock" easily and detailedly. Thank you.
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