Could anybody tell me about Virtual Clock??

[evesjh77]

Please tell me about "Virtual Clock" easily and detailedly.
Thank you.

 

[kumar_eee]

Virtual clock is the clock which is logically not connected to any port of the design and physically doesn’t exist. A virtual clock is used when a block does not contain a port for the clock that an I/O signal is coming from or going to. Virtual clocks are used during optimization; they do not really exist in the circuit.

Virtual clocks are clocks that exist in memory but are not part of a design. Virtual clocks are used as a reference for specifying input and output delays relative to a clock. This means there is no actual clock source in the design. Assume the block to be synthesized is “Block_A”. The clock signal, “VCLK”, would be a virtual clock. The input delay and output delay would be specified relative to the virtual clock.

 

[evesjh77]

Thank you Very Much.
I'm exactly understand about Virtual Clock.
Thank you so much.