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my code is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mishee is
port(clk,rst:in std_logic;
bw:in std_logic ;
rcvim:out std_logic;
rma:in std_logic_vector(4 downto 0);
test:out...
I changed the code.
I can not but lead output
It(test<=CONV_INT2STDLV(circlex(0),8);) was clear when I synthesis code!!!!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity migmig is
port(clk,rst:in...
my codlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ghj is
port(clk,rst:in std_logic;
bw:in std_logic ;
-- a:out std_logic ;
-- test:out integer range 0 to 105;
g:out std_logic_vector(6...
hello,
Why the following testbench code in the first clock d1, d2 are value
And the second clock a, b
library IEEE;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use...
hello,
Why the following testbench code in the first clock d1, d2 are value
And the second clock a, b
library IEEE;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL...
Re: Image processing and VHDL
You must first create a text file
example:It was a image of the text file conversion,in matlab:
[sourcepic,phatsource]=uigetfile(('*.jpg;*.tif;*.png;*.gif;*.bmp'),'select a picture');
A=imread([phatsource sourcepic]);
B=rgb2gray(A);
% B=edgeim;
disp('Image file...
i am changing.
variable row:integer range 0 to 177:=0;
variable clm:integer range 0 to 287:=0;
but It still can not synthesized.I do not know what's the problem.When I synthesize the code.
Synthesis and any error would not have stopped 46%
my code:
library ieee;
use...
if(row<177)then
if(clm<287)then
i am changing but it not synthesis.it stop in 46
- - - Updated - - -
if(row<177)then
if(clm<287)then
i am changing but it not syntesis. it stop 46%
help me please
my code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity detectsphere is
port(clk:in std_logic;
bw,rst:in std_logic;
a,wr:out std_logic
);
end;
architecture detect of detectsphere is
type im1x is array(0 to 286) of std_logic...
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