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[SOLVED] Fatal error in modelsim

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esielec

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help me please
my code:


Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity detectsphere is
port(clk:in std_logic;
     bw,rst:in std_logic;
      a,wr:out std_logic
      );
      end;
      
      architecture detect of detectsphere is
      type im1x is array(0 to 286) of std_logic;
      type im2x is array (0 to 176)of im1x;
      signal im:im2x;
      type state_machine is(s1_rcv,s2_rcv);
      signal state:state_machine:=s1_rcv;
      
      begin
     
     process(clk)
      
      variable row:integer range 0 to 176:=0;
      variable clm:integer range 0 to 286:=0;
      
      begin
      if (clk'event and clk='1') then
                if(rst='1')then
                        if(state=s1_rcv) then
                                if(row<286) then
                                        if(clm<176) then
                                                im(row)(clm)<=bw;
                                                clm:=clm+1;
                                        else
                                                clm:=0;
                                                row:=row+1;
                                        end if;
                                else
                                        state<=s2_rcv;
                                        wr<='1';
                                        clm:=0;
                                        row:=0;
                                end if;
                        elsif(state=s2_rcv)then
            
                                if(row<286)then
                                        if(clm<176)then
                                                a<=im(row)(clm);
                                                clm:=clm+1;
                                        else
                                                clm:=0;
                                                row:=row+1;
                                        end if;
                                else
                                        wr<='0';
                                        clm:=0;
                                        row:=0;
                                end if;
 
                        end if;
                else
                        wr<='0';
                        
                end if;
    
        end if; 
                
      end process;
     
    end;



testbench:


Code VHDL - [expand]
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-- Copyright (C) 1991-2012 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
 
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "08/24/2015 11:06:15"
                                                            
-- Vhdl Test Bench template for design  :  detectsphere
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 
library IEEE;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
 
library std;
use std.textio.all; --include package textio.vhd
 
ENTITY detectsphere_vhd_tst IS
END detectsphere_vhd_tst;
ARCHITECTURE detectsphere_arch OF detectsphere_vhd_tst IS
constant MAX : integer := 256*256-1;
 
-- constants                                                 
-- signals                                                   
SIGNAL wr: STD_LOGIC;
SIGNAL bw : STD_LOGIC;
 
COMPONENT detectsphere
    PORT (
      clk:in std_logic;
     bw,rst:in std_logic;
      a,wr:out std_logic
    );
END COMPONENT;
 
   SIGNAL rst :  std_logic := '0';
    SIGNAL clk :  std_logic := '0';
    SIGNAL a :  std_logic := '0';
    
--Outputs
--period of clock,bit for indicating end of file.
signal endoffile : bit := '0';
signal d1,d2,intt : integer:=0;
 
--signal dbus: std_logic_vector(7 downto 0) := x"00";
 
--------------------------------------------------------------------------------------------
 
function CONV_STDLV8bit_2INT(ARG: std_logic) 
return integer is
variable int: integer:=0;
variable tmp: std_logic;
begin
    int :=0;
    tmp := ARG;
     
        if (tmp ='1') then
            int := 1;
        else 
            int := 0;
        end if;
     
    return int; 
end CONV_STDLV8bit_2INT;
--------------------------------------------------------------------------------------------
function CONV_INT2STDLV(ARG: INTEGER) 
return STD_LOGIC is
variable result: STD_LOGIC:='0';
variable temp: integer:= 0;
begin
    temp := ARG;
    
        if ((temp mod 2) = 1) then
            result := '1';
        else 
            result := '0';
        end if;
    
    return result; 
end CONV_INT2STDLV;
--------------------------------------------------------------------------------------------
    constant PERIOD : time := 20 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 30 ns;
 
BEGIN
    i1 : detectsphere
    PORT MAP (
-- list connections between master ports and signals
    a => a,
    bw => bw,
    clk => clk,
    rst =>rst,
    wr =>wr
    );
CLOCK: PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
    END PROCESS;
    
tb: PROCESS
    BEGIN
        rst <='0';
        wait for 60ns;
        rst <='1';
        wait for 1312us; -- will wait forever
        
    END PROCESS;
    
reading : process
    file infile : text is in "img.txt"; --declare input file 1987
    
    variable inline : line; --line number declaration
    variable dataread1 : real;
    begin
        wait until clk = '1' and clk'event;
        
            if (not(endfile(infile))) then --checking the "END OF FILE" is not reached.
                    readline(infile, inline); 
                    read(inline, dataread1);
                    d1 <=integer(dataread1);
                bw <= CONV_INT2STDLV(d1);
--                  readline(infile2, inline2); 
--                  read(inline2, dataread1);
--                  d2 <=integer(dataread1);
--              b <= CONV_INT2STDLV(d2,8);
            else
            
          endoffile <='1';
            end if;
        
    end process reading;
 
--write process @negative edge
writing : process
    file outfile : text is out "outimgvhdl.txt"; --declare output file 1987
    variable buff_out : line; --line number declaration
    begin
        wait until clk = '0' and clk'event;
        if(endoffile='1') then --if the file end is not reached.
            intt <= CONV_STDLV8bit_2INT(a);
             
            write(buff_out, intt);  
            writeline(outfile, buff_out);-- write line to output_image text file.
             
         
             
        else
            null;
        end if;
    end process writing;                                       
END detectsphere_arch;



error in modelsimaltera:

# Time: 626560 ns Iteration: 1 Instance: /detectsphere_vhd_tst
# ** Warning: (vsim-100) Real literal has no dot.
# Time: 626580 ns Iteration: 1 Instance: /detectsphere_vhd_tst
# ** Warning: (vsim-100) Real literal has no dot.
# Time: 626600 ns Iteration: 1 Instance: /detectsphere_vhd_tst
# ** Fatal: (vsim-3421) Value 177 for row is out of range 0 to 176.
# Time: 626620 ns Iteration: 1 Process: /detectsphere_vhd_tst/i1/line__21 File: A:/poroje/tabdil matlab be vhdl_poroje/1/detectsphere.vhd
# Fatal error in Process line__21 at A:/poroje/tabdil matlab be vhdl_poroje/1/detectsphere.vhd line 37
 
Last edited by a moderator:

FvM

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** Fatal: (vsim-3421) Value 177 for row is out of range 0 to 176.

Almost self-explanatory when looking at the code, I think. You'll either increase the range or don't allow a value > 176.

Code:
variable row:integer range 0 to 176:=0;
variable clm:integer range 0 to 286:=0;
 
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esielec

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Code:
if(row<177)then
										if(clm<287)then
i am changing but it not synthesis.it stop in 46
Capture.JPG

- - - Updated - - -

Code:
if(row<177)then
										if(clm<287)then
i am changing but it not syntesis. it stop 46%
Capture.JPG
 

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You do realize that if you compare row<177 it will execute the then statement when row = 176 and if that has a row := row + 1; it will overflow the range to row 177, which you have defined as range 0 to 176.
 

esielec

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i am changing.
Code:
	  variable row:integer range 0 to 177:=0;
	  variable clm:integer range 0 to 287:=0;
but It still can not synthesized.I do not know what's the problem.When I synthesize the code.
Synthesis and any error would not have stopped 46%
my code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity detectsphere is
port(clk:in std_logic;
     bw,rst:in std_logic;
	  a,wr,sum:out std_logic
	  );
	  end;
	  
	  architecture detect of detectsphere is
	  type im1x is array(0 to 286) of std_logic;
	  type im2x is array (0 to 176)of im1x;
	  signal im:im2x;
	  type state_machine is(s1_rcv,s2_rcv);
	  signal state:state_machine:=s1_rcv;
	  
	  begin
	 
	 process(clk)
	  
	  variable row:integer range 0 to 177:=0;
	  variable clm:integer range 0 to 287:=0;
	  
	  begin
	  if (clk'event and clk='1') then
				if(rst='1')then
						if(state=s1_rcv) then
								if(row<177) then
										if(clm<287) then
												im(row)(clm)<=bw;
												sum         <=bw;
												clm:=clm+1;
										else
												clm:=0;
												row:=row+1;
										end if;
								else
										state<=s2_rcv;
										wr<='1';
										clm:=0;
										row:=0;
								end if;
						elsif(state=s2_rcv)then
			
								if(row<177)then
										if(clm<287)then
												a<=im(row)(clm);
												clm:=clm+1;
										else
												clm:=0;
												row:=row+1;
										end if;
								else
										wr<='0';
										clm:=0;
										row:=0;
								end if;

						end if;
				else
						wr<='0';
						
				end if;
	
		end if;	
				
	  end process;
	 
	end;
 

K-J

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Maybe it takes a while for synthesis to come up with the 50,799 flip flops (50,799 = 287*177) which are the dimensions of the 'im' matrix.

Kevin
 

esielec

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It was true.
But since the code was first written synthesis?:bang:
 

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Vivado synthesis completed synthesis in about 30 seconds, and used LUT RAM to implement the array. As it was smart enough to determine that it could be implemented as RAM that probably explains the speed.

XST isn't necessarily the smartest tool to infer RAM from code so, it might be hanging just like Quartus. I don't have Altera tools installed so I can't make any comparison, and given that the XST has been running for 10 min I suspect it's just having problems with 50K of FFs in the array.
 

esielec

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thank you.
It should look for other methods of image processing to be Fpga:thumbsup:
 

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