esielec
Newbie level 6

help me please
my code:
testbench:
error in modelsimaltera:
my code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity detectsphere is port(clk:in std_logic; bw,rst:in std_logic; a,wr:out std_logic ); end; architecture detect of detectsphere is type im1x is array(0 to 286) of std_logic; type im2x is array (0 to 176)of im1x; signal im:im2x; type state_machine is(s1_rcv,s2_rcv); signal state:state_machine:=s1_rcv; begin process(clk) variable row:integer range 0 to 176:=0; variable clm:integer range 0 to 286:=0; begin if (clk'event and clk='1') then if(rst='1')then if(state=s1_rcv) then if(row<286) then if(clm<176) then im(row)(clm)<=bw; clm:=clm+1; else clm:=0; row:=row+1; end if; else state<=s2_rcv; wr<='1'; clm:=0; row:=0; end if; elsif(state=s2_rcv)then if(row<286)then if(clm<176)then a<=im(row)(clm); clm:=clm+1; else clm:=0; row:=row+1; end if; else wr<='0'; clm:=0; row:=0; end if; end if; else wr<='0'; end if; end if; end process; end;
testbench:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 -- Copyright (C) 1991-2012 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to -- suit user's needs .Comments are provided in each section to help the user -- fill out necessary details. -- *************************************************************************** -- Generated on "08/24/2015 11:06:15" -- Vhdl Test Bench template for design : detectsphere -- -- Simulation tool : ModelSim-Altera (VHDL) -- library IEEE; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use IEEE.MATH_REAL.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; library std; use std.textio.all; --include package textio.vhd ENTITY detectsphere_vhd_tst IS END detectsphere_vhd_tst; ARCHITECTURE detectsphere_arch OF detectsphere_vhd_tst IS constant MAX : integer := 256*256-1; -- constants -- signals SIGNAL wr: STD_LOGIC; SIGNAL bw : STD_LOGIC; COMPONENT detectsphere PORT ( clk:in std_logic; bw,rst:in std_logic; a,wr:out std_logic ); END COMPONENT; SIGNAL rst : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL a : std_logic := '0'; --Outputs --period of clock,bit for indicating end of file. signal endoffile : bit := '0'; signal d1,d2,intt : integer:=0; --signal dbus: std_logic_vector(7 downto 0) := x"00"; -------------------------------------------------------------------------------------------- function CONV_STDLV8bit_2INT(ARG: std_logic) return integer is variable int: integer:=0; variable tmp: std_logic; begin int :=0; tmp := ARG; if (tmp ='1') then int := 1; else int := 0; end if; return int; end CONV_STDLV8bit_2INT; -------------------------------------------------------------------------------------------- function CONV_INT2STDLV(ARG: INTEGER) return STD_LOGIC is variable result: STD_LOGIC:='0'; variable temp: integer:= 0; begin temp := ARG; if ((temp mod 2) = 1) then result := '1'; else result := '0'; end if; return result; end CONV_INT2STDLV; -------------------------------------------------------------------------------------------- constant PERIOD : time := 20 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 30 ns; BEGIN i1 : detectsphere PORT MAP ( -- list connections between master ports and signals a => a, bw => bw, clk => clk, rst =>rst, wr =>wr ); CLOCK: PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; tb: PROCESS BEGIN rst <='0'; wait for 60ns; rst <='1'; wait for 1312us; -- will wait forever END PROCESS; reading : process file infile : text is in "img.txt"; --declare input file 1987 variable inline : line; --line number declaration variable dataread1 : real; begin wait until clk = '1' and clk'event; if (not(endfile(infile))) then --checking the "END OF FILE" is not reached. readline(infile, inline); read(inline, dataread1); d1 <=integer(dataread1); bw <= CONV_INT2STDLV(d1); -- readline(infile2, inline2); -- read(inline2, dataread1); -- d2 <=integer(dataread1); -- b <= CONV_INT2STDLV(d2,8); else endoffile <='1'; end if; end process reading; --write process @negative edge writing : process file outfile : text is out "outimgvhdl.txt"; --declare output file 1987 variable buff_out : line; --line number declaration begin wait until clk = '0' and clk'event; if(endoffile='1') then --if the file end is not reached. intt <= CONV_STDLV8bit_2INT(a); write(buff_out, intt); writeline(outfile, buff_out);-- write line to output_image text file. else null; end if; end process writing; END detectsphere_arch;
error in modelsimaltera:
# Time: 626560 ns Iteration: 1 Instance: /detectsphere_vhd_tst
# ** Warning: (vsim-100) Real literal has no dot.
# Time: 626580 ns Iteration: 1 Instance: /detectsphere_vhd_tst
# ** Warning: (vsim-100) Real literal has no dot.
# Time: 626600 ns Iteration: 1 Instance: /detectsphere_vhd_tst
# ** Fatal: (vsim-3421) Value 177 for row is out of range 0 to 176.
# Time: 626620 ns Iteration: 1 Process: /detectsphere_vhd_tst/i1/line__21 File: A:/poroje/tabdil matlab be vhdl_poroje/1/detectsphere.vhd
# Fatal error in Process line__21 at A:/poroje/tabdil matlab be vhdl_poroje/1/detectsphere.vhd line 37
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