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I need somehelp to set design constraints ( on timing, capacitance ,area etc). I have written a constraints.g file and i am reading it using read_sdc command in cadence encounter( RTL compiler) . Can someone suggest me the commands that need to be written to set these constraints.
i have tried generating a vcd file using command
$dumpfile("testd.vcd");
$dumpvars;
but i cannot find a vcd file that is generated.
I have a .gz file though.
Can you please elaborate the methods.Any useful links will also do.
Thanks you
I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler.
I have made 3 folders. Work,RTL(where all .v files are stored), Library(which has slow_normal.lib).
In the work folder i type...
I dont want to generate it using LFSR, i want to use $random function of verilog to generate a random 8 bit data stream. I have generated random integer from 0 to 255 using the following code.
Can anyone suggest methods to convert this into 8 bits
My code :
initial
begin
integer num...
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