Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by efundas

  1. E

    Will Specman die for Vera as Borland die for Micro$oft?

    Do we always have to just keep updating ourselves with new langauges, will there be a stable and standard language ever.
  2. E

    Janick Bergeron was sold to Designware

    It is usually seen that only verification jobs are moved out. So there is always shortage of communication in the projects, resulting in degrading quality. Probably sooner or later moving out only the verification activity may be stooped or probably the entire project might be moved away.
  3. E

    Who's goin to dominate the nex-generation HDL world?

    I think we need some common language and environment which can be used right from design phase to system level validation. ie, code the design in language X, develop the test environment in language X, interface that supports the usage of already developed test environment in language X to be...
  4. E

    Netlist Simulations - Interview question

    Do we still do any gate level simulations??? In our company gate-level simulations was long abandoned. Today all we do is STA and formal verification.
  5. E

    what is the meaning of system gates ?

    But there is no fixed gate size for logic cells such as LUTS etc. It varies depending on the way it is used. So how can there be a fixed system gate count for a FPGA.
  6. E

    VHDL and Verilog which one you use more often?

    I was using VHDL almost 2years back, now I am working only in verilog.
  7. E

    VHDL/Verilog Editor under Linux

    gvim linux vhdl gvim, nedit and emacs are some of the VHDL/Verilog editors available for linux. I prefer gvim.
  8. E

    Parameters influencing choice of FPGA

    Xilinx are the best but do have lot of drawbacks compared to others. I tinnk altera is picking up but it may take quite sometime for them to overtake xilinx.
  9. E

    VCS, NC-Verilog and Modelsim, which is the best simulator??

    debussy modelsim Modelsim is most easiest to use and the best wrt the features, as per what I have used
  10. E

    How to avoid using clk buffer ?

    But that constraint will disable the use of the BUFG0. My problem is that for a particular I do not want to use the clock routing. If I disable the use of BUFG0, it will take some other buffer.
  11. E

    How to avoid using clk buffer ?

    How to avoid clk buffer I am synthezing my design for Xilinx device. I find that one of my input signal which is not a clock is being through the global clk buffer. How can I force the synthesis tool to not use the clk buffer for this input.
  12. E

    The explanation of false paths

    What about the async paths(eg, path from one clk domain to another async clk domain). don't we consider them also as false paths in synthesis.
  13. E

    Static Timing Analysis - two good STA presentations

    Re: Static Timing Analysis Here they are. I had downloaded these files from here itself.
  14. E

    How to know the net name connecting port/pin in DC shell?

    do we have a general DC script or the order in which the commands are to be issued .....
  15. E

    problem of IC5.0 installed on Redhat 7.2

    If you don't mind could you give the details to change the dsplay settings. I remember struggling out with the xconfigurator once and was not able to do it.
See more

Part and Inventory Search

Back
Top