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Recent content by eda4you

  1. E

    matlab & cadence co-simulation

    analoglib simulinkcoupler hi drabos! could you send some more information about the cadence simulink interface because i coudn't find any doc about that issue. Which ic version supports that tool? thx
  2. E

    slow CMFB clipping output

    after a sc charge transfer all nodes (also the the cm) have to (re-)settle. hence the cm loop has to settle at least as fast as the dm loop for sc circuits. in continous time circuits even 5 ttimes as a rule of thumb.
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    Questions about SNR of delta sigma ADC

    Re: delta sigma adc snr also noise (but i don't think you put it into your simulation), ron of switches, clock feedthrough or charge injection, lousy cm-feedback of the opamp. Also saturation of the opamp, limited gbw, sr, finite gain, ...
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    how to simulate

    spice esd eds simulation in spice-spectre is quite difficult because you must have quite good models of the esd device, which I never got during my profession. It is also not necessary since a full snap-back will destroy your ic. Furhter ESD simulation are made with device simulators. I made...
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    matlab & cadence co-simulation

    matlab co-simulation cadence I used in aptiva various matlab functions a few years ago to analyze simulation results of an adc. Which version of ADE or ic respectivley, supports matlab? Further is a matlab tollbox necessary for cosimulation`. thx
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    Questions about Matlab code for sampling and aliasing

    Re: matlab help please you have already implented an aliasing example. now you are sampling every 10th zero crossing of the sinusoid signal. for instance set interval now to 950 and you will see a sinus with a frequency of 50.
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    what function do the five serial transistors act as ?

    it is a simple diode. maybe the lenght of the overall transistor is to large for the drc. I had some problems once time and ahd also to split it into shorter ones and connected in series. the interesting was that it was noit realy a design rule violation, it was only give because the transistor...
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    The status at Cadence about VAMS software

    in my company we worked about 2 man-years for modeling a complex soc system. as larger the system get the more fault and netlist errors occured, although the blocks work fine, but simulating the whole system is unimpossible! the design support helped us, but what made me wundering is that the...
  9. E

    Where do your knowledge mostly come from?

    a combination of daily work, paper and book reading, less university courses (mostly only the very basic, however it is very important to know this), and of course colleges. the most i learnt of false working and defect circuits.
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    Help, Which structure is right(ESD protect circuit)?

    i made the same experience. the problem within layout (a) is that you have to ignore the drc errors. Normaly you can help yourself in setting a rectangel above the device with drc ignore. that is the way i dit it. but to be sure you should contact your device or process engineers.
  11. E

    phase margin of phase lock loop

    Normaly the pahse margin is only computed for a linear model of the pll. as mentioned before a step response of the loop filter gives the correct answer. i am sure you will find in literature the equation where you can e.g. compute the phase margin with the first two overswing amplitudes.
  12. E

    PLL Phase margin at low frequency

    phase margin pll hi, its o.k. the pahse margin is here 90 degrees. at moderate frequencies the zero forces a increase in phase before the lowest low pass pole decrease again the . It seems that you used a normal 2nd order pll filter. the vco of the pll causes a 90 degree phase shift, and one...
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    difference between the indian and international editions?

    Re: difference between the indian and international editions Hi, Ive bought some books from india and compared it with us/europe ones. There is no difference between both releases. The only one is a different ISBN number and the color of the front is another, e.g. Johns/Martin. It is a one to...
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    The low value of drop out voltage in LDO

    Re: Question about LDO hallo greenhand, the trick with very low dropout regulators is that a charge pump is used. This charge pump enables a gate voltage higher than vdd. So the pass transitors can be kept in linear region.
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    i want to ask the progress when FPGA boot

    when fpga boot Look for Xilinx Boot EPROm like XCF08P and so on. This is a special eprom which sends the fpga the serial init datas. ciao
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