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Recent content by ed271828

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    How do timing constraints work for a bus interconect?

    Suppose I have a number processors connected to a shared bus interconnect, as well as a number of slave devices. In a real design, how is something like that clocked/timed/constrained. I can't imagine that they all use the same clock domain. Can anyone provide some insight, what would an actual...
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    ModelSim waveform printing question

    Thanks, but my supportnet account doesn't allow this :P
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    ModelSim waveform printing question

    Is there anyway to set the FONT SIZE for wave form prints? Some values on waves usually get scaled down too much to make them readable. Thanks!
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    It's a very simple on-chip bus protocol with a well defined naming convention. IIRC, you assert STB and CYC to initiate a bus request and wait for ACK to appear at least 1 cycle later. Ed
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    Fields for PhD in RF and Microwaves

    Re: phd suggestion you don't seem to be a very natural researcher then!! come on!!.. go and work for a few years, take on some projects, and eventually you'll be more motivated and have an idea about what to do. how about spending some time reading the latest journals, but dig into the ideas...
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    Principles of Asynchronous Circuit Design - A System Perspec

    Re: Principles of Asynchronous Circuit Design - A System Per mm is this legal !???
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    What's the best VHDL/Verilog/SystemVerilog editor?

    notepad++ system verilog I've switched from UltraEdit to notepad++ lately. I used to use emacs, but I eventually found that the VHDL/Verilog modes got in the way, and I also found it became a hassle to configure how tabs were handled. I'd rather do all the indentation myself (ie: relpace tab...
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    systemC issue: errors LNK2001 and LNK1120

    error lnk2019 _sc_main bump. Has this been resolved, I'm having the same issue. I also (strongly) believe I've linked the library properly.
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    chinese language is difficult to learn ,but chinese people

    Re: chinese language is difficult to learn ,but chinese peop I wouldn't mind learning chinese, but consider that I have absolutely no language skills - although, I already speak English and French fluently. If I were to take a single semester long course in Mandarin, how well would I be able...
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    Design Compiler to target FPGAs or DC FPGA?

    I understand it is possible for Design Compiler to target FPGA devices, just as it would a standard cell library. Could someone please elaborate on the differences between this and Synopsys' DC FPGA compiler, which I assume produces more optimal results for FPGAs? I am wondering if I wanted to...
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    Bluespec SystemVerilog ???

    No one has used this?..
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    Bluespec SystemVerilog ???

    Have any of you used BSV? It seems like an interesting product and I would like to hear some feedback. Thanks, Ed
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    SystemVerilog synthesizable subset - current vendor support?

    Re: SystemVerilog synthesizable subset - current vendor supp The synthesizable subset of SystemVerilog is NOT an IEEE standard. I looked through solvnet yesterday regarding DC FPGA, and have another question. Does it's support for SystemVerilog relie on (V)HDL Compiler and not DC FPGA...
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    Inferring TRUE Dual-Port RAM ???

    inferring rams That's clearly what they want us to do, but it's a pain in the @ss when you want to generate a parameterizable design. Design portability is also an important issue.
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    Inferring TRUE Dual-Port RAM ???

    inferring true dual port ram Hi, It seems that (some?) synthesis tools do not allow us to infer TRUE Dual-Port RAM, eg: two independent read and write ports. Is there a particular reason for this? Do you know of any synthesis tools that actively supports this? I don't believe that either...

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