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Recent content by ecijun

  1. E

    How to get Pad center point

    I'd like to get PAD center point in layout automatically for package, pls give me some advice, skill or some tool? thanks .
  2. E

    can Verilog and matlab cosim be used in NC-verilog

    including verilog in matlab Can I use Verilog and matlab cosim in NC-verilog
  3. E

    DFT for core with BIST memory

    bist memory 1 No 2 Yes, some eda tool can insert the MUX.
  4. E

    Memory Modeling for MBISTArchitect

    Yes, I can.
  5. E

    why scan chain is deleted before placement and reconnected..

    The design has problem.
  6. E

    Memory Modeling for MBISTArchitect

    very good!!! Thank you.
  7. E

    Ip block library(*.db,*.lib,*.lef) generation

    use library generation tool
  8. E

    Comparison of Setup and Hold timings with removal and recovery timings

    Latch Timings In Latches we will check the setup and hold time.You can check the sta user guide.
  9. E

    synopsys Error: no license found contact server?????????

    command "lmgrd -c" to start license
  10. E

    TAP controller design specification

    DFT Thank you, It is a very good document.
  11. E

    Does the EDA vendor's tool support the Latch-based design?

    Latch-based Design Which P&R tool supports latch based design?
  12. E

    Does the EDA vendor's tool support the Latch-based design?

    Does the EDA vendor's tool support the Latch-based Design including syn, dft, P&R, sta?
  13. E

    Verilog simulation with Virtuoso and cadence tools

    You need check .simrc file.
  14. E

    open source Processor verilog code

    power-down mode leon 2 Did anybody download the code?
  15. E

    How does the buffer reduce delay ?

    Buffer You can read Rabaey's book
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