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Recent content by echoangel9111

  1. E

    Ring Oscillator Calculation Question

    Hi, I have this 65 stage ring oscillator that has a clk frequency of say X MHz. If have a -10% decrease in Idsat for nmos and -12% decrease in Idsat for pmos, what would be the new clk frequency of the ring oscillator? Assuming parasitics doesn't change. Is it possible to calculate? thanks
  2. E

    Yellow,Red,White Cables to Analog Monitor Input Converter

    yellow monitor input Is there anything on these resources/websites I could look at ?
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    vlsi: cell yield calculations

    Hello people, i was wondering who can help me solve this a single transistor DRAM cell with a total storage of cap 10fF is refreshed at frequency of 1MHz using 5v supply. The read circuitry will detect voltages more or less than vdd/2. Due to processing variations, the cell leakage current...
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    How to compute 9 point DFT using only blocks that can do 3 point DFT?

    I want to compute 9 point DFT using only blocks that can do 3 point DFT. How do i do this?
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    Synthesis and Place and Route Differences

    Hello, I was wondering what factors contribute to inaccuracies between the timing as reported by Synopsys and actual timing after Place and Route? What can I do in general to fix these inaccuracies?
  6. E

    [SOLVED] All Interview Questions - Open Thread - Please Contribute

    8051 related interview question If you live on a tropical land, how would you create ice? without any modern technologies use your imagination, you can do anything you want using any resources on the island
  7. E

    help with understanding flip flops

    Hello, I am very confused on understanding hold constraints on a positive edge trigger flop. I know it is Tcq + Td >= T hold but when you introduce a clock slew , how does this work?? aka pipelines are there any diagrams people can show?
  8. E

    newbie question to DSP and frequency domain

    Hello, I see some textbook representation of frequency using X(jw) and some other cases X(w). Can someone clarify this
  9. E

    how to design 8 to 3 encoder

    Hello I have to use NAND , NOR and INVs, is there any way I can minimize gates used? say inputs are from z0 - z7 and outputs are A B C A = Z4+ z5 + z6 + z7 B = Z2 + z3 + z6 + z7 C = z1 + z3 + z5 + z7 is this technically wrong? what if I input an incorrect sequence such as 11111111
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