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how to design 8 to 3 encoder

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echoangel9111

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Hello

I have to use NAND , NOR and INVs,

is there any way I can minimize gates used?

say inputs are from z0 - z7 and outputs are A B C

A = Z4+ z5 + z6 + z7
B = Z2 + z3 + z6 + z7
C = z1 + z3 + z5 + z7

is this technically wrong? what if I input an incorrect sequence such as 11111111
 

enjunear

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Sudarsan_EDA

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There are many ways to construct "8 to 3 encoder"

But you are not specified any don’t care condition are applicable or not?

can you send your inputs & output details in the truth tables?
 

ljcox

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This Digital Logic Gates Part-III might be helpful in figuring out how to simplify logic gates into NAND/NOR/INV equivalents. BTW, this is how many arcade games in the early days were built... lots of NAND, NOR and inverter DIPs.

That reference is quite good. It is similar to my paper that is attached.

One way to detect whether 2 or more inputs are = 1 would be to use XOR gates.

I have attached an example of a 3 input NOR gate. The output is only true if only one of the inputs is true.

This could, in theory, be expanded to 8 inputs.
 

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  • 3 input XOR.gif
    3 input XOR.gif
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enjunear

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ljcox, nice refernce information. The XOR appraoch would simplify things, but echoangel stated that they have to use NAND, NOR and INV's (sounds like homework, to me!). Otherwise, that's the way I'd go at it.
 

ljcox

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ljcox, nice refernce information. The XOR appraoch would simplify things, but echoangel stated that they have to use NAND, NOR and INV's (sounds like homework, to me!). Otherwise, that's the way I'd go at it.

We may be wasting our time as the Op has not posted recently.
 

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