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help with understanding flip flops

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echoangel9111

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Hello,

I am very confused on understanding hold constraints on a positive edge trigger flop.

I know it is Tcq + Td >= T hold

but when you introduce a clock slew , how does this work?? aka pipelines

are there any diagrams people can show?
 

electronics_kumar

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echoangel9111 said:
Hello,

I am very confused on understanding hold constraints on a positive edge trigger flop.

I know it is Tcq + Td >= T hold
what do you mean by Tcq and Td...explain the terminlogy...
 

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