Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by E-goe

  1. E

    [SOLVED] Op amp to rescale A/D input

    What about adding an offset circuit to shift the lower range and apply gain to clip to upper range? E-goe
  2. E

    FPGA VHDL code for VSP2560PTR (CCD)

    Hi Scanman, Dark correction is an offset correction method. Another sensor/pixel non-ideality one can calibrate for is PRNU ( Pixel response Non Uniformity ) caused by gain variation between the pixels. In order to correct for PRNU/ gain mismatches one can do the following: 1. Allow system...
  3. E

    FPGA VHDL code for VSP2560PTR (CCD)

    Hi Scanman, Typically CMOS Image sensors do CDS ( correlated double sampling ) on-chip. So a opposed to CCD there is no need to do CDS off-chip. In CMOS sensors CDS is done to reduce the pixel KTC noise of the pixel and reduce FPN of the pixel. Depending on the CMOS Image sensor one still...
  4. E

    Nonlinear PGA in CMOS Image Sensor

    Hi, For a new project we are trying to increase the dynamic range of the CMOS image sensor by using 2 PGA's. One with a low gain and one with a high gain. The low gain PGA will be used for high illuminant scenes and the high gain PGA will be used for the low illuminant scene. So I need a...
  5. E

    Power supply sinking capability

    power supply sinking Hi, For the moment I am using a power supply ( custom made ) which uses an OPA2277 to control a Darlington Transistor ( BD679 ). Basically the custom made power supply unit is a linear regulator. So this supply can source my required current to the DUT, but a problem...
  6. E

    Including package parameters in simulation testbench

    Hi, I my current project I'm designing an analog output amplifier to drive an off chip capactive load of around 15pF @75MHZ. Now I want to incorporate as much parasitics as possible in my testbench. So I started to see what really matters. I came up with the following important package...
  7. E

    Kickback in a sample and hold

    Hi, Let me describe my problem: 2 basic sample and hold stages ( driver-switch-sample cap ) are cascaded. The first sample and hold cap is sampled first and the switch to the other sample and hold at that time is open ( not conducting ). After that the switch of the first sample and hold is...
  8. E

    TCAD software in Ubuntu

    ubuntu tcad Hi, Which programs do you guys use for TCAD simulations? Tsupreme, Centaurus ...? I want to use Tsupreme. Can anybody give me some links where I can download Tsupreme. I want to run it on Ubuntu. Also if someone knows some good tutorial of Tsupreme, I' ll be glad to read this...
  9. E

    Microwave studio capacitance extraction

    Hi, I want to use MWS to extract the mutual capacitance between 2 metal lines. Is someone familiar with this or knows some relevant documentation you can share? Regards E-goe
  10. E

    Troubleshooting LVDS link between sensor and digital board

    Hi, Let me first describe my testsetup ( see attachment ). The testsetup to debug the LVDS link between the sensor and the controller board contains 3 boards: 1.Digital controller board: this board contains an FPGA ( Spartan 3E ). This FPGA sends commands (CMOS levels )to the sensor, which is...
  11. E

    lvds receiver characterisation

    Hi For a certain project I designed an LVDS receiver to be compliant with the LVDS TIA-644 standard. I f the chip comes back from the fab we need the characterize this LVDS receiver. So we are currently working on the testboard. We need to test the TIA specs of the LVDS receiver. One of...
  12. E

    What kind of amplifiers and architectures are used for LVDS receiver?

    Re: LVDS receiver Thanks ericzhang, The link to the documents you gave all disccus LVDS transmitters. Neither off them describe an LVDS receiver. As in the TIA/EIA -644-A the specs for an LVDS receiver are mentioned as: Common mode can vary 0.05V and 2.35V and the differential voltage can...
  13. E

    What kind of amplifiers and architectures are used for LVDS receiver?

    Hi all General question: What kind of amplifiers did you guys see in an LVDS receiver. The LVDS receiver needs to translate theLVDS input signal to an CMOS differential signal. What should be a suitable architecture for it? PMOS/NMOs input differential amplifier or something more advanced...
  14. E

    Best practices for clock tree distribution

    Hi, how to define a clock tree. What are the things we need to take care of... Best practices for clock tree distribution. I'm especially intrested in analog clock tree distribution as I currently need to route critical signals to serializers over 25mm. And the control signals need to arrive...
  15. E

    Information about powerclamps in IC design

    Hi Can somebody provide me with some information about powerclamps in IC design? What is it doing,why is it needed, how to implement it Also any papers, related chapters of E-books ...
See more

Part and Inventory Search

Back
Top