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Congestion in general referred to routing. Placement congestion is due to overlap of standard cells, it is called overlapping rather than called as congestion.
Routing congestion is difference between supplied and available tracks. A track is nothing but a routing resource. Tracks fill...
Re: STA
Useful is nothing but skewing the clock inorder to fix the timing violations. you can borrow the positive slack from the previous path and can fix the violation for the present one.
how to solve reg2reg hold
you cannot reduce the clock skew to zero because on chip variations.
virtual clock is used to constrain the input to output (timing path) in your design.
Re: MS or M.Tech in VLSI
Hi Kumar_eee,
even i want to know about institutions or universities which are offering MS or M. Tech in VLSI abroad.I am in INDIA now.
thnxs
cts
Hi Priya_j,
DRV violation include three things
1.Max Cap
2.Max Tran
3.Max Fanout
First, one should fix Max cap, that you can do by including Max Cap statement in cts specification file.You assign cap value for a buffer by using this statement.Cap value you decide by looking int SDC...
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