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Recent content by dreamteam

  1. D

    tackling the problem of offset voltage and CMRR

    You could also increase size of input transistor to reduce mismatch and then reduce offset. But them in WI could also be usefull.
  2. D

    question about Bandgap simulate

    In this case of bandgap, it's better opening the loop on both inputs and apply +0.5/-0.5 ac voltage source on it. It's the best way to simulate the PM/GM. You can also use vcvs to really open the loop.
  3. D

    Looking for a CMOS current source

    Re: A robust CMOS current source this is a feedback loop. M38 and m39 are connected to ensure a negative feedback loop. This is why this scheme is stable. Without M38 you dont have a current source. See razavi or p allen book to understand.
  4. D

    the buffer in the low dropout regulator

    How can you do a LDO with source follower ???? To get a very low drop out you must have a PMOS at the output. Everybody saying that a NMOS could be use don't have LDO problem or had Native NMOS device.
  5. D

    Help me design an opamp for the output of DAC

    Re: Opamp Design Help.. To get the maximum output swing, try to keep only Vds sat. 50mV will be hard to get.... Try a class AB, or an Rail to Rail output stage and choose W/L in order to have a low Vds sat. A two stage opamp could match but you couldn't cascode.
  6. D

    does anybody understand this POR circuit?

    That's right. In fact the temperature behavior is due to the structure. The crossing point of this POR is very stable in temperature. Unfortunatly, the crossing point is for vdd=Vbg=1.2V. If you try to fix another value, the crossing point will have a lot of spread.
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    How does this circuit work??

    Hello everybody, Transistors M1, M2, M3 are a current substractor circuit. with this kind of circuit you can drive your push pull output stage with the differential pair output and it's complementary signal genrated by the substractor. The connection between M5 and M3 would probably makes and...
  8. D

    Bandgap reference ( output voltage variation)

    In your bandgap equation, K= R2/R1 * ln(n) where n is the ratio between bipolar. So your are independant of resistor variation in case of you've matched your resistor in the layout.
  9. D

    Why contact and via have exact size ?

    contact and via size This must be exact size because if they only said that is minimum size, you could make a big via (we can imagine 1u/1u). In this case, metal stress will be too important and can have negative effect on your design. In all fundary, via have exact size.
  10. D

    Why using transistor sizes larger than the minimum length?

    transistor size Choosing 100/2 instead of 50/1 is better for matching devices. Mismatch depend on area of the transistor. 100x2=200, 50x1=50 so your transistor area is 4 times bigger, so your mismatch will be 4 times smaller.
  11. D

    How to Detect Bad Battery

    bad battery voltage Battery is a current source, so you have to check the voltage through a load. Checking only voltage without load won't be enough to detect bad Battery.
  12. D

    How to suppress a regulator ripple?

    About regulator ripple Agree with VVV, be aware of your LDO stability and check your phase margin. What decoupling capacitor do you use ? Is the value enough ?
  13. D

    Loop stability in low dropout regulators

    simulate stability of ldo Gabriel Rincon Mora wrote a lot of papers about your problem. Simple search on the net will give you a lot of answer. Look especially in IEEE journal of solid state circuits vol.33 no 1 january 1998. Ka Nang Leung also write papers about LDO. Simulate only the 2...

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