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ac resistance vs dc resistance
Hello everyone,
I'm using Ansoft Q3D to do some extraction tasks and found out that Q3D gives lower AC resistance value than DC resistance value. This really confused me because all what i learned tell me that the resistance of a conductor @ high frequency is...
ansoft designer layout gerbers
Dear Folks,
When I place a coupled stripline circuit component STLCPL2 (I was going through the differential pair example in Designer manual) in Ansoft Designer schematic windows, a dialog popped up asking whether or not to merge layers. Could anyone tell me...
Dear Folks,
When I place a coupled stripline circuit component STLCPL2 (I was going through the differential pair example in Designer manual) in Ansoft Designer schematic windows, a dialog popped up asking whether or not to merge layers. Could anyone tell me what does it mean?
I looked through...
Hi, eexuke,
The delay of a gate typically is determined by
- the input signal slope
- output resistance
- load capacitance
Now let's ignore the first item. Output resistance (Rout) is roughly inverse proportional to its
size.
Load capacitance = the diffusion cap of gate it self (Cdiff) + wire...
tsmc 0.25um spice parameters
Hi, visualart,
Click on any entry and pull down to the bottom, you'll see spice3f level 8 (corresponding to Hspice level 49) device model, which is essentially BSIM3v3.
I never heard that BSIM3v3 is too simple to simulate a circuit.
I think it would be accurate to distinguish sizing up a "transistor" and sizing up a "gate".
-- When you size up a CMOS gate ( which consists NMOS PDN and PMOS PUN), you increase its driving capability but also increase the capacitive load to previous gate. This will affect the total delay of...
First, "wider wires are more susceptive to skin effect" is not accurate. Increasing wire width/height for sure decreases wire resistance, which in turn reduced RC delay. It's only that increasing wire width/height larger than 2*skin_depth won't reduce wire resistance anymore. Also notice that...
how to post a question in synopsys solvnet
Dear all,
I have two questions on synopsys tools.
1. What's the difference between "W" releases and "vW" releases? For example,
"pp_vW-2004.12-SP2" and "PP_W-2004.12-SP2", which are two releases of PowerCompiler.
2. Synopsys has a bunch of power...
Re: about physical design
Hi,
I would suggest the following steps
1) Read one or two books on physical design
There're two e-books talking about physical design in this forum:
An Introduction to VLSI Physical Design
h**p://
and
Algorithms for VLSI physical design automation
h**p://
The...
Michael Flynn has a book talks a lot of floating point arithemtic.
https://www.amazon.com/exec/obidos/tg/detail/-/0471412090/qid=1098395796/sr=8-1/ref=sr_8_xs_ap_i1_xgl14/103-8900713-2898269?v=glance&s=books&n=507846
If you can not afford to buy the book, you can go to his lab homepage. The...
I think this is related to logic styles. For example, dynamic logic uses less transistors than static CMOS but the former consumes much more power.
However, no explicit formula exists.
Re: WavePipeline
Professor Wayne Burleson of UMass did a lot of research on wave pipeling. He had a very good survey paper on this topic.
Wave-pipelining: A tutorial and survey of recent research
https://citeseer.ist.psu.edu/59714.html
Re: REVERSE engineering
h**p://www.sanguine.com.cn
But interesting I couldn't access the site from US.
Their flag tool is called "ChipSmith", and its second generation "Picasso".
The founder of the company is from Fudan University, to which they had a very close relationship. Actually some...
Re: CVS and HDL code
Well, concerns to the size of source code of ASIC project, CVS is actually good. But remember you NEED a CVS guru in your team, otherwise it would be a mess. SUBVERSION is a promising replacement for CVS although I haven't tried it.
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