why top-most metal for clock and power?

[eexuke]

Dear all,
Usually we use the top-most metal for our clock and power, but I have learned
1)top-most metal usually has largest capacitance
2)top-most metal usually has smallest capacitance
then RC delay of top-most metal cancel out each other for large C and small R.However, the wider metal is more suspective to skin-effect which will increase resistance when frequence reaches GHz domain.
So why we still use top-most metal for clock/power?

Many thanks in advance!

 

[rprince006]

I think that is because clock/power/reset signals are critical to physical design.
generally top-layer matel is used to route these signals, so that they don't need to go through any via's/bridges, and routing is easy to control and predict, and routing/layout calculation/evaluation is simpler and more accurate.

 

[nxing]

The reason of using top-most medal for power line is because they have the smallest resistance(I don't think delay is an issue for power line). But I don't know why for CLOCK signal, hope somebody have the answer for it

 

[au_sun]

clock has to be routed to all the FFs in the design,
so they should be routed with top metal layers that has
less resistance, that can handle large loads,bcos these layers
has to handle large capacitive loads during clock routing.

 

[kxchorus]

I dont think clock wire should be routed at the top metal. In large scale of design, clock tree is often needed and will not restricted it to use only top metal.

 

[rakeshnunna]

Hi all,
I think we will use top-most metal for clock bcoz, it will be better to have a thick metal layer for clock since there will be more switching activity for the clock net.

 

[rprince006]

Hi guys,

I think the top matel is for nets which have highest priority, need more flexibility, and for wide nets.

Power/clock lines need to be very wide, and uniformly distributed on the wafer.
Reset is usually timing critical, so it may be also on the top level.

Delay is stem from parasitic RC's. It is easier to use thick matel in top layer for
reducing R and C.

 

[minhle]

In my opinion, power routing are always placed on the top-most layer since it has least resistance and capasitance => less load and power drop.
for the smae reason, the clcok nets are routed on those layer to obtain the least parasitcs => less delay.

 

[don_quixote]

First, "wider wires are more susceptive to skin effect" is not accurate. Increasing wire width/height for sure decreases wire resistance, which in turn reduced RC delay. It's only that increasing wire width/height larger than 2*skin_depth won't reduce wire resistance anymore. Also notice that without buffer insertion, distributive RC delay is quadratic with the wire length. So reducing wire capacitance/resistance is really important. In general, we reduce wire resistance by adopting better conductor (copper) and fat wires. We reduce capacitance by adopting better inter-layer dielectric materials.

Second, clock/power network have a hierarchical structure. They goes from the top level all the way to the substrate. So image in a 3D view it's really like a upside-down tree. You need fat wire at the top level because you need to supply huge current to thousands of transistors on the substrate. Image a highway system, the trunk need to be thick to support a large communication flow. Does it make sense?

 

[au_sun]

hi,
anybody having any papers, material stuff regarding clock tree and power routing
metal details pls upload, it i wll be great help

thanx in advance
au_sun

 

[xworld2008]

usually, PG use top metal, for clock don't use top metal, just use double width of signal.

 

[power-twq]

if we place power and clock signal on top-most metal layer,

the interference between clock signal and other signal is

minimized because of far distance between clock signal and other

signal, at the sam time, power and ground line can provide

some shielding for clock signal. in synchronous circuit,

keep clock signal's clean and integrity is predominant.

Dear all,
Usually we use the top-most metal for our clock and power, but I have learned
1)top-most metal usually has largest capacitance
2)top-most metal usually has smallest capacitance
then RC delay of top-most metal cancel out each other for large C and small R.However, the wider metal is more suspective to skin-effect which will increase resistance when frequence reaches GHz domain.
So why we still use top-most metal for clock/power?

Many thanks in advance!