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Recent content by dll_fpga

  1. dll_fpga

    Onsite opportunities for VLSI Engineers

    Hi , I coud'nt find any onsite opportunities for VLSI professionals.Please guide me where/what can i search for? Any links/job sites dealing with onsite opportunities. Is it really possible to get some onsite opening... Will they prefer people from home country first? Any help will be appreciated.
  2. dll_fpga

    hexadecimal addition subtraction multiplication division without a calculator

    hi fvm, i mean some shortcuts for hexadecimal arithmetic
  3. dll_fpga

    Headecimal debugging

    Hi Please let me know how hexadecimal debugging can be made easy in a simulator.Please let me know some tips /tricks or links which explain shortcuts on hexadecimal arithmetic
  4. dll_fpga

    hexadecimal addition subtraction multiplication division without a calculator

    Please let me know some links/tutorials to do hexadecimal addition subtraction multiplication division without a calculator.
  5. dll_fpga

    Checking 4k boundary crossing in AHB/AXI by an interconnect/bridge

    Will the interconnect know the addrress map and it check combinationally by comparison? Please help me to find an equation/code to check how can 4k crossing be prevented.? Please provide some example.
  6. dll_fpga

    How to calculate the aligned address

    Is it required to be always a power of 2 can it be 0 5 10 to access 5 byte info?
  7. dll_fpga

    How to calculate the aligned address

    Please help me understand the concept of aligned address and how to calculate it? I saw the below equation from AXI spec Aligned_Address = (INT(Start_Address / Number_Bytes) ) x Number_Bytes.
  8. dll_fpga

    Formula for Depth calculation for any FIFO (syncronous or asyncronous )

    ya.Whatever computed above is unitless,this has to be mutiplied by the data width to get the actual size in bit. FIFO size = write bandwidth /read bandwidth maybe be true only if write side frequency is very high as compared to read side frequency. ie:By the time first clock edge of read edge...
  9. dll_fpga

    why do we use barrel shifter

    barrel shifter is nothing but cascaded mux whose select can be controlled for almost any sort of shifts
  10. dll_fpga

    Formula for Depth calculation for any FIFO (syncronous or asyncronous )

    For complex cases,as indicated by permute,we need to consider the burst size and the effect of subsequent burts. FIFO size = sigma [i=1 to n burst] ( w(t) - r(t) ) For simple systems [subject to below mentioned assumptions] FIFO size = Time to read / Time to write. ---(1) 1/T = f...
  11. dll_fpga

    Formula for Depth calculation for any FIFO (syncronous or asyncronous )

    permute, From your original example, i could see that the, only requirement is to backup 990kb of data in a sec.So Depth is not only the factor,that we need to consider. That means depth*width = 990kb. I think any solution to the above equation can correctly implement the requirement. Please...
  12. dll_fpga

    8b/10b encoding approach for serial links

    It is more easy to implemement in lookup table.
  13. dll_fpga

    Formula for Depth calculation for any FIFO (syncronous or asyncronous )

    Assumption made: word size is same on read side and write side. eg: wr 100Mhz and rd 10Mhz FIFO size is (100 -10 )*10E6 Assumption made: word size is same on read side and write side. Then again the question comes write and read number is to be computed in which time frame? Also i think we can...
  14. dll_fpga

    Formula for Depth calculation for any FIFO (syncronous or asyncronous )

    Hello Permute and KJ, Thanks for the post. Permute, I think instead of peak bandwidth we need to consider the peak throughput(actual amount of DATA that is written/read in a given time frame). . >>Look at a 1Mbps data stream and a processor capable of processing data at 100Mbps. It would...
  15. dll_fpga

    Meaning of Memory notation 800MHZ *2 *16bit

    hello FVM, I'm confused whtr its a 32 bit location . According to you its 16 bit organization with double data rate... Below are some details i got from the data sheet: AXI access is limited to 32bit at 32 bit boundary No byte or 16 bit access or odd address access

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