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Recent content by dkk1980

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    Xilinx IO Constraints

    hi thanks for the reply. What clock is used for the device that receives the data from the FPGA? -- 25 Mhz Internally generated clock
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    Xilinx IO Constraints

    Hi all, The OFFSET constraint does not optimize paths clocked by an internally generated clock. We have an external input clock of 50 Mhz, which is divided by a DCM internally to generate a 25 Mhz clock. The internal logic works with 25Mhz clock. How do we apply the OFFSET constraints...
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    Designing a SD Card Host Controller

    Re: SD Card Controller yanzixuan Thanks for pointing that out. i will go through the same. Thanks dkk
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    Designing a SD Card Host Controller

    Re: SD Card Controller Nuwan I think you should consider the pricing also. The spec will cost you 1000 USD. A general membership will cost you 2000 USD. IF you buy the spec and become a member in 90 days 1000 USD paid towards the spec will be deducted from the membership fee. I think with a...
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    Designing a SD Card Host Controller

    Re: SD Card Controller Hi Nuwan Thanks for the reply. The physical connectivity of both microSDHC and microSDXC are the same. Both use 8 pins. I think there is no difference b/w SD and microSD other than the physical dimension. The physical i/f of SD has 9 pins while that of microSD has 8...
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    Please guide to me for VHDL coding

    go through the syntax of the language first, then start writing small programs.
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    Designing a SD Card Host Controller

    Re: SD Card Controller Hi Nuwan Thank you very much for the reply. I would also like to know what is the latest specification version. Is it 3.0? It supports SDXC ? We are planning to have a microSDXC controller. Is there any difference b/w SDHC and SDXC in the physical interface ? or there...
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    Designing a SD Card Host Controller

    Hi, Simplified specification of SD Card is available for free in sdcard.org. Is it possible to develop a SD card Host Controller using this simplified specification or one need to have the complete spec ? Thanks and regards dkk
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    Does Virtex6 support 3.3v IO operation?

    Virtex-6 IO Does virtex6 supports 3.3v IO operation? if no what is the alternative for connecting 3.3v IOs to it? Thanks dkk
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    From spartan-3 to Virtex-5

    Hi, In spartan-3 a slice contains two LUTs(4 input) and two flip-flops, where as a V5 slice contains four LUTs (6 input)and four flip-flops. So if my logic consumes 100 slices in Spartan-3, then how many slices will it consume in V5? Thanks dkk
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    Timing analyses using Xilinx Timing analyzer

    Re: Timing analyses You can apply a PAD to PAD constraint in ISE and see whether it meets. dkk
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    numeric_std or std_logic_unsigned

    Hi, Which library should i use for unsigned numbers ? 1. numeric_std or 2. std_logic_unsigned Why? Thanks dkk
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    timing simulations during FPGA design flow

    hi saikat thanks for the reply. After PAR, through STA we will be able to know whether all the timing parameters (like setup, hold time etc) are met or not. Then what additional information do we get by running timing simulations after PAR? Thanks
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    timing simulations during FPGA design flow

    after PAR, if all the timing constraints are met, is it necessary to do timing simulation ?
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