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Hi All,
I tried to run simple sv queue example with ius82_s014 and I observed weird behavior while calling function using void'().
Following is the complete example:
module class_queue;
class trans;
string myname;
int data;
int d_size;
int state;
function new(string name = "")...
Hi,
I am trying to instiate the interface inside .v file and passing that interface instance in other two separate .v files.
Following are the files and content inside files. I am using ius6.2 version to run using ncsim command.
1. my_tb.v -> inside ./project/v_files/
`include my_intf.sv...
Hi nand_gates,
I didn't get you actually. Won't T-FF will give the output always as 1? Because the XOR output will always be 0 (D and Q are same). Please let me know if I am wrong?
Thanks,
Dipak
Hi Sp3,
I your unknown ckt is D-FF then you must consider there will be delay of 2 clks, after that you will get D value as your final output. I am attaching the ckt diagram.
Regards,
Dipak
Re: System Verilog
Hi Preddy,
You can download SystemVerilog LRM or you can visit www.asic-world.com or else you can have "SYSTEMVERILOG FOR VERIFICATION - A Guide to Learning the Testbench Language Features" for verification purpose.
--Dipak
irun assertion switches
Hi boardlanguage,
I am very thankful to you. Aah it worked finally...
I tried the $shm_open and $shm_probe....
Thank you very much.
--Dipak:D
simvision dump file
Hi boardlanguage,
Thanks for your kind support....
Now, I am running the verilog code and assertion(SVA) using Cadence IUS 6.11 ncsim and then for waveform I am using Simvision... The similar problem I am facing in this case also.
Let me know if you are aware of this...
$shm_probe
Hi boardlanguage,
See I am using Questa for simulation. The qverilog command compiles (vlog), optimizes (vopt), and simulates (vsim) Verilog and SystemVerilog designs in a single step. It combines the compile, elaborate, and simulate phases together, as some users may be accustomed...
shm_probe ac
Hi boardlanguage,
I tried the following thing in my code(assert_ack.sv):
###############################################
module hahahahahaha;
my_assertion1 : assert property ( @(posedge clk) disable iff ( !rstn )
req |-> ##1 ack; // expect ACK signal 1-cycle after REQ
)...
shm_probe
I have written assertion to verify certain timing protocol. I am using cadence's simvision tool for waveform analysis. But I don't know how to add the assertions in the simvision waveform viewer. Is there any setting for this?
Please help me.
Thanks in advance.
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