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Recent content by devop

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    Question about TSMC memory

    anyone can help ~~~
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    Question about TSMC memory

    Thanks a lot Jbeniston I have a other quesiton about the rf2sh and ra2sh rf2sh not have layer 50(DMSRM) and the ra2sh has that , why they are different ?
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    Question about TSMC memory

    Hi All I have question about the TSMC 013 RAM, It seems here are two RAMS , one called SRAM (such as ra2sh) and the other one called “Register File”(such as rf2sh). What’s the difference of these two blocks? Best Regards Devop
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    Do i need Isocell for a signal going from AON domain to SWD(off) domain?

    hi， check your library , think about a AON cell driving a transfer gate , you need the iso cell
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    how to reduce net delay with out disturbing its length, driver and sink

    go to the top thick metal.
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    jtag in P&R phase - what I should pay attention to

    Re: jtag in P&R phase what's jtag cell??? is it a stdcell? what's special for the cell implementation?
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    factor for de-skewing of memory

    de-skew of the memory Hi , what's "factor for de-skewing of memory" in p&r ?????? thanks
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    jtag in P&R phase - what I should pay attention to

    jtag in P&R phase hi , if here's jtag in the chip? what I should pay attention to when process the P&R phase, thanks in advance
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    power mesh calculation questions ??

    Here's power mesh calculation from a paper, but I'm not very clear about that, Iblock= Pblock / Vddcore  Current supply from each side of the block: Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2 ---------(1) Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2  Power strap...
  10. D

    LOCKup & SYNC Registers.

    hi here's a lockup latch question here~~~~ If we don't add the latch in che chain, in test mode,if here's hold problem, p&r tool will add the delay cell here, so the latch is not necessary am I right????????????????
  11. D

    clock uncertainty vs clock jitter

    pre cts setup: uncertainty = jitter+ margin+skew post cts setup: uncertainty = jitter + margin just as Fahmy said, The Jitter is a quantitative measure for the clock uncertainty it's a really clock ,output of pll.osc~~~~~~
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    an old CTS question - sizes of clkcells for clock tree

    thanks koggestone I consider the question in another way, case 1, 10 cells , they scatter in a big area, the ocv for the whole path will be better, just for a certain cell ,you are right ,Bigger Buffers (i.e Big W ) will decrease Variations. what's your opinion?
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    an old CTS question - sizes of clkcells for clock tree

    I am confused here, case 1, 10 smallest buf1X connet in series to drive a load case 2, 1 biggest buf64X drive the same load I think case 1 will be better in OCV? what's your opinion?
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    an old CTS question - sizes of clkcells for clock tree

    upup one more question,would I use regular buffer instead of CLKBUF if the skew is not a big issue??
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    how to calculate the power mesh

    I want to konw what I should take into consideration when doing the floorplan especially the power mesh calculation can you help me?
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