an old CTS question - sizes of clkcells for clock tree

[devop]

an old CTS question

Hi guys:
why we dont use the smallest and largest clkcell when building clock tree?
we usually us 3x 4x....16x clockbuf ,what about you?
thanks a lot

 

[devop]

Re: an old CTS question

Hi guys:
why we dont use the smallest and largest clkcell when building clock tree?
we usually us 3x 4x....16x clockbuf ,what about you?
thanks a lot

can anyone kindly share the experience??
do you use 1x or 64x clockbuf in you design?

 

[devop]

upup
one more question,would I use regular buffer instead of CLKBUF if the skew is not a big issue??

 

[koggestone]

My Intuitive guess is

smallest clkbufs - are more sensitive to Process variations , hence clock skew(OCV)
issues.

Largest clkbufs - have more Current , Hence Electromigration(EM) /Reliability
related issues , (besides too much of Power Consumption).

 

[devop]

smallest clkbufs - are more sensitive to Process variations , hence clock skew(OCV)
issues.


).

I am confused here,
case 1, 10 smallest buf1X connet in series to drive a load
case 2, 1 biggest buf64X drive the same load

I think case 1 will be better in OCV? what's your opinion?

 

[koggestone]

I am confused here,
case 1, 10 smallest buf1X connet in series to drive a load
case 2, 1 biggest buf64X drive the same load

I think case 1 will be better in OCV? what's your opinion?

case 2 has Less OCV .
Refer to famous Pelgrom's 1989 paper on Mismatch.
**broken link removed**
Bottom Line is - Variations are inversely proportional to Transistor Area (W.L).
Bigger Buffers (i.e Big W ) will decrease Variations.

Hence u see all those Microprocessor Global clk design guys and Anolog
designers will love to use bigger Transistors to decrease mismatch at the
expense of more power dissipation.

 

[devop]

I am confused here,
case 1, 10 smallest buf1X connet in series to drive a load
case 2, 1 biggest buf64X drive the same load

I think case 1 will be better in OCV? what's your opinion?

case 2 has Less OCV .
Refer to famous Pelgrom's 1989 paper on Mismatch.
**broken link removed**
Bottom Line is - Variations are inversely proportional to Transistor Area (W.L).
Bigger Buffers (i.e Big W ) will decrease Variations.

Hence u see all those Microprocessor Global clk design guys and Anolog
designers will love to use bigger Transistors to decrease mismatch at the
expense of more power dissipation.

thanks koggestone

I consider the question in another way,
case 1, 10 cells , they scatter in a big area, the ocv for the whole path will be better,


just for a certain cell ,you are right ,Bigger Buffers (i.e Big W ) will decrease Variations.

what's your opinion?