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Recent content by design_oriented

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    [SOLVED] Tcl workshop from Synopsis

    Got it. Will close the thread. There was an older thread that mentioned it was available on the Synopsis website so asked. Thanks.
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    Block level closure guidelines

    Hi, Are there any good tutorials for block level rtl to gds2 closure? Thanks
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    [SOLVED] Tcl workshop from Synopsis

    Hi, Anybody has the tcl workshop from Synopsis? Thanks.
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    Hold time measured on previous cycle compared to setup time

    Why is the hold time in PrimeTime measured on the previous rising edge compared to the setup time?
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    Analog design project ideas

    Hi Guys, I am a digital ASIC design professional and want to get into analog IC design. Any suggestions/ideas for a challenging, relevant project that I could start off with? Should I go for PLL's or ADC/DAC's or something else? Any ideas/suggestions are appreciated. Thanks.
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    To find number of cells which are unplaced after placement?

    Try using the dbget and dbquery commands similar to my reply to your other post asking for clock buffers.
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    How to find number of clock buffers in a given rectangular region of core?

    You can try using the saveClockBuffers or the displayClockMesh command. You can specify the clock domain for which you need the buffers. ---------- Post added at 07:24 ---------- Previous post was at 05:51 ---------- Something along these lines (with the db commands): Replace the coordinates...
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    Data required on how IR-Drop analysis done at block level.

    "Dynamic IR drop are independent of frequency whereas static IR drop vary with clock frequency. " Do you mean to say the opposite of the above? Apache Redhawk is a much better graphical tool for IR drop analysis.
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    What does metal stack option 8m5x2y2z mean ?

    5x means not just width but metals M2,M3,M4,M5,M6 have the design rules of Mx (spacing, area, etc.) which is specified under the Mx section in the DRM. Similarly 2y will have M7 and M8 rules as My. This is based on TSMC rules. This nomenclature may be different for different foundries.
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    HSPICE Subckt question

    Hi Guys, In my SPICE .spi file, I have a NAND gate subckt by the name U1234. This NAND gate is is defined in the .spice file and has multiple transistors, one of them being NMOS x1234. How can I measure the voltage at the drain of this transistor in HSPICE? The gate node is defined as...
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    DRCs in signoff tool which are not seen in PNR tool

    The DRC error differences between PNR tool and signoff tool depend on the quality of your LEF file (for SOC flow). If you start seeing enclosure errors, spacing errors, etc. in your PNR tool flow but not in your DRC signoff tool, it is a good idea to check your LEF file to see if all the rules...
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    HSPICE 1E-18 CAP value

    Hi Guys, In one of my hspice netlists I am getting a node cap of 1e-18 F to GND. This value is showing up from the o/p of the inverter to GND. I see another 1e-18F value from the input of the second inverter to GND. The circuit is one inverter feeding another inverter. Where could this 1e-18 F...
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    Primetime vs. Spice correlation and plots

    Hi Guys, Has anybody here done PT vs HSPICE correlations? Can anybody point me to some basic tutorials? I was reading this paper "CCS vs NLDM Comparison Based on a Complete Automated Correlation Flow between PrimeTime and HSPICE" and was not able to understand what is meant by endpoint path...
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    Are MultiVT Filler cells only NWell or complete MOS devices?

    Hi Guys, Are multi Vth FILLER cells only Nwell implants or are they full PMOS devices with VDD and VSS taps? As threshold voltage gets mentioned, I assume they have a gate and diffusion regions. If they are just Nwell implants on P substrate i.e. diodes, what is meant by threshold voltage...

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