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Recent content by delay

  1. delay

    functional and formal verification

    formal and functional verification In EDA industry a subset of formal verification known as logic equivalence check is used mostly for digital designs although formal techniques are being applied to analog designs and mixed signal circuits as well but BDDs and Kirpke graphs are treated as...
  2. delay

    tutorial on conformal (verplex)

    cadence conformal tutorial Here's a very basic tutorial. http://www.chiptalk.org/modules/wfsection/article.php?articleid=3
  3. delay

    functional and formal verification

    formal verification Functional verification is usually exhaustive, checking all boundary conditions to get a golden RTL, it is prior to synthesis. It is generally done using a tool that does timing verification such as NCSIM/SimVision and ModelSim. Formal verifcation tools compare RTL golden...
  4. delay

    what is synthesizable

    Means the HDL code can be translated into physical circuits such as shift registers, counters etc. which may or may not be functionally correct. Most synthesis tools for FPGAs do not support real numbers.
  5. delay

    What are the hot subjects in R&D groups these days?

    I have been offered a PhD seat for research on low energy protocol design for WSN SoC. Is this a good area?
  6. delay

    Dose any FPGA support reconfiguration?

    All FPGA's are reconfigurable with the exception of fused typed such as those from Actel.
  7. delay

    partial and dynamic reconfiguration

    Dynamic means run time, while system is operative. Partial means part of the resident resources are reprogrammed while other system areas are unaltered.
  8. delay

    modes of behavioral simulation in ISE/Modelsim

    Hello Gurus, I wrote a state machine in VHDL and then simulated it using ISE and ModelSim in three different ways within ISE: A) New Source -> VHDL Test Bench, entered test vectors in the process statements B) New Source -> Test Bench Waveform, generated a behavioral .vhw file from wave forms...
  9. delay

    Modelsim simulations in 2 ways - they mismatch

    I have a mismatch in Modelsim behavioral simulations using 1) VHDL testbench in ISE and 2) manual entry of stimuli. While the vector inputs are same in time and values in both cases, the output, however, is different. The manual simulation seems working as designed but the testbench based...
  10. delay

    how to partition or architecture?

    Do front-end and back-end partitions.
  11. delay

    What is the responsibility for a PCB designer?

    In the United States typically PCB designers are not college graduates, they have experience and lots of it. Normally the hardware engineer, the one who captures the schematic and designs the system sits with the layout guru about SI and EMC conformity issues. The PCB designer knows the gimmicks...
  12. delay

    Good univty for VLSI postgraduation

    You should prefer Western countries over India for further education.
  13. delay

    How does the job market in RF design look like in the US?

    Re: Job in USA You may land on a Swedish company's payroll such as Saab Ericsson in the USA. Such company's always look for their native speakers, however, you may have to change technologies to get such job i.e., you may not exactly find a job that fits your educational/experience profile.
  14. delay

    Guidance on Post Graduation in VLSI from Germany

    vlsi at germany ISLI - UK
  15. delay

    What is Germany like and how does the job market look like?

    Re: Jobs in Germany? How about Soest or Paderborn?

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