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hi thanks for ur reply
actually i have doubt regarding simulated result...i have written the code for an 8*8 pipelined multiplier..afterthat i have done a compilation successfully, but now i want to check out the simulated output for an this multiplier..to view the simulated waveform , i...
Re: help in verilog code
hi
thanks for ur reply, actually this is the help i'm expecting from ur people .. i have downloaded the pipelined 8*8 multiplier code from net, but while i simultaing that ,im not able to get simultaed result, and also i didnt know how to force the input..so if u...
hello everybody
i'm deepa...i need help from the people who know about MYCAD tool..and also i have some doubt in that tool..can u clarify that?
while drawing layout what grid size i have to select..is this default one or will be changed based on tecnologies..is grid size common for all...
help in verilog code
hello everbody
i need help from verilog, if anybody having the smulated result both input and output for an 8*8 mutiplier using verilog , can u send it to me?
thanks,
deepa.v
hi mujju THis is deepa.. reply me immediately
hi mujju how r u? i hope u will be fine?
do u remeber me? iam deepa2, working in chennai, i hope u remeber me? unfortunatley my old id was corrupted, so i lost ur id, throgh this edaboard, i found ur id ,and i mailing u now, i hope u remember...
hi frnds,
this is deepa belongs to this group..i need one help ..if any one know how to do the animation pattern program for race problem in digital logic circuits, if so plz respond..pls send me that program , either using matlab or vhdl, but i need result in animation pattern..
thanks....
Thanks guys...i think i have to refresh a lot, before i can get into Verilog coding... it looks like simple coding, but works very differently... tell me some books i can refer so i can start to understand what to code, and what not...
Code to find GCD...
I want the code to find GCD by foll. method..
gcd(a_in,b_in,a_out,b_out)
{ if((b_in==0)||(b_in==1))
{ a_out = a_in;
b_out = b_in;
}
else
{ gcd(a_in,ain%b_in);//recursive function
}
}
This is the logic in...
Thank You very much FvM and echo47...Thanks for your help...
Added after 2 minutes:
Please help me with the modulus code as well.....Once again,thanks for your effort guys...
I am using Xilinx to develop some code....The code finds power of two given no.s....Dont know where the mistake is...Finds some synthesis error.....
ERROR:Xst:528 - Multi-source in Unit <power> on signal <rsta>
Sources are:
Signal <rsta> in Unit <power> is assigned to GND
ERROR:Xst:528 -...
Re: DOUBT IN VERILOG( ANY BODY KNOW THE SYNTAX FOR SINE &
hi frnd,
thanks for ur reply.........i saw that pdf file...but can u help me how can i use this in my project to generate sine and cosine function, is this in built function in xilinx? i couldnt able to understand to proceed further...
HI EVERY BODY
THIS IS DEEPA ...DOING PROJECT IN VERILOG...FRNDZ HELP ME TO DO MY PROJECT WELL...
ANY BODY KNOW THE SYNTAX FOR SINE AND COSINE FUNCTION IN VERILOG?
PLS REPLY ME...
THANKS......[/b]
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