Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
One block needs to work at 960M Hz (such as USB2 Rx) but in which the internal voltage regulator only has 1M Hz bandwidth and 6M Hz UGF. Apparently, above 6M Hz, large decap helps to make power stabe without regulator. Please help to explain this? Thanks.
Hi guys, I made a mistake that designed a TIA For differential input current signal from PD (see the attachment 1.)
But obviously, only one current signal from PD exits for A TIA input (see the attachment 2). So my question how to converge the single input signal to differential input based on...
Hi Erikl, I think we made a mistake at the beginning. The transimpedance gain of TIA should not be compared with its openloop gain by just so simple way. Smaller openloop gain still can have large TIA gain.
My TIA transfer function is wrong. It should be (for first order system)...
OK. So, do you mean mean that if I want to design a 80dB ohms transimpedance gain of TIA, I can both design a 90dB OR 70dB main amplifier (OPAMP in TIA) to achieve that? Thanks.
Cox
Hi FvM, do you mean that the closed loop gain of TIA can be achieved larger than its open loop gain? But it doesnot make sense since Acl=Ao/(1+f*Ao) and f=1/Rf
----> Acl=Rf/(Rf/Ao+1). Can you explain a little more details about that? Thanks.
Cox
Hi Dominik, yeah decreasing the size will make the second pole larger but smaller L degrades gain. I will read the second method you mentioned. Thank you!
Cox
Hi, I am using the classic folded cascode one stage OTA for the specification: gain=70dB, phase margin=60 degree and Unit gain frequency=90M Hz.
load capacitor =50p F
1. How to increase phase margin without decreasing gain, unit gain frequency and also without increasing load capacitor...
Hi Erikl, Thank you! The paper is "A 5 Gbps Low Noise Receiver in 0.13μm CMOS For Wireless Optical Communications", Behrooz Nakhkoob, RFIC,2012. The paper is attached below. As I said, Aol=250=48dB and Acl=25k ohms=80dB. Pls help me have a look. Thank you!
Best,
coxstreet
LvW, yes. The closed loop gain ideally is Rf while the classis opamp is equal to the open loop circuit. So the closed loop bandwidth mainly depends on the shunt resistor.
Thank you for your explanations.
1. So, if I want to achieve the tia characteristic as same as the curve of the TRANSIMPENDANCE AMP CHARACTERISITC , I need to design the
the open loop frequency response as same the top curve of the TRANSIMPENDANCE AMP CHARACTERISITC, not the one-frequency...
Thanks for your answer.
The output impedance of open loop is small so that it does not degrade the TIA gain and this is clear now. But I have several points I donot understand:
1. The OPA380' open loop gain is 120dB but it stay only 100Hz and after that it will drop, not stays 120dB until its...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
