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Well, I redraw the sch. like this, the bias circuit is not shown. You mean with an ac disturbance on AVCC, there is a noise current on the left hand leg, and MP6 will copy this noise current to the right hand, which will inject to node M. And now the node M is a noisy node, which cancels AVCC's...
Hello, I have met a LDO circuit as shown, the first stage is a symmetric op and MP4 is the pass device. With cap C1 added, the PSR has significant improvement, but I'm confused on how to choose C1's Capacitance, I simulate it when C1 is too large or small, it has no effect. I simulate it with 1V...
The book says: "CFF is to feed forward small signals from Vo to feedback node VFS. This introduces an in-phase zero ZFF that helps save phase near the unitygain frequency of the system. "
But the base of Q1(VA) is inverting input, VA and Vo are out of phase, so CFF should introduce a...
In a Vth reference circuit shown below, do I have to do a stability analysis？I simulated the circuit in virtuoso, and when I break the loop at point A, the loop phase starts from 0°, which means it is a positive feedback; while I break the loop at point B, the loop phase starts from 180°. The...
I have just simulated a simple schematic in ADS, the load ind(2nH) and cap(1pF) resonate at 2.52GHz (both of them are ideal component). The DC bias of the nmos is 0.4V, input power is 10dBm, so it is biased at class-c operation. But the simulated current of the nmos is a sine wave(even...
well, I'm still confused about the current Ib'. (1). If Ib' is from M5, does it mean that the current of M5 will be larger than that of M6? (not equal？) (2). If Ib' is from discharging CL, it means that the charge moves from the upper plate of CL to the right plate of Cc, but they are just one...
yeah, an opposite in polarity charge accumulates on the other plate, so there's current flowing into the other plate, but where does this current(Ib') come from?
Hi~
In my circuit there are some inductors and transformers using EMX models extracted from layout, and I meet a problem doing corner analysis using ic5141. The corner analysis failed, It looks like it's because I didn't add up EMX model library in corner analysis setup but I don't know how...
But since current IB is flowing from the plate of Cc which connects to Node 1, the other plate of Cc(i.e, Vout), has no charge accumulation, how can Vout rise up to Vdd?
In the book Analog Design Essentials, the author says that "This SR appears at the output as the VGS6 is still about constant. Indeed, transistor M6 still conducts as if nothing has happened!" But,why? Since M4 is on, the voltage of Node 1 will ultimately become low, so M6 would turn off and...
could you tell me how do R and Cbs form the low pass filter? I draw a picture and i1 is the current produce by M1. It doesn't seem to be the low pass filter example in the right half of the picture since node Y is floating?
Hi, I saw a common use of the body-source resistor in RF power amplifier designs, what's the role of it? Somebody says it can block rf signal from entering the body of the cascode transistor, but if the voltage of node X is swing, the voltage of node Y will also swing since the resistor R is...
Hi, I’m new to EMX and I have some questions:
1. In EMX user manual, it says :”By default, EMX attaches a voltage source from each label in the structure to the ground plane.” and the infinite ground plane is beneath the bottom layer. I think the ground plane is beneath the bottom layer so...
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