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I have a good understanding of DFT and ATPG and have used Tetramax a fair amount. However, I don't remember the scripts and files you use for Tetramax. Could someone provide an overview of the scripts/files it uses and a simple example that generates stuck-at tests and writes them out as a...
Every ATPG has to fault simulate the vectors they generate or they would
never complete test generation for any design.
They don't modify your netlist file. They work on their own binary internal
representation of the netlist in memory.
Why would you not do timing analysis?
Your design may not operate correctly if you don't do timing analysis on parts of it. So you should do timing
analysis on the whole design.
You don't need to use a single clock to shift the scan chain.
Your scan chain connector could add lockup latches on clock domain boundaries. Alternatively
you could sort the flip-flops so those in each domain are together in the chain and schedule
the clock pulses so those closest to scan out...
You need to provide a better description of the chip DFT facilities.
It could be that it uses pins to control the DFT logic or operates through JTAG.
If it uses pins to control the DFT logic there are most like the following pins:
test/functional pin
shift/no shift pin
test clock pin
scan...
I am developing a threaded application to run on a MAC that needs to run on many UNIX platforms. Apple has a function (OSAtomicTestAndSetBarrier) that takes a index into an array of bits, sets the bit and returns whether the bit was set previous. This function is uninterruptible and used to...
As you are talking about analog circuits there can be an almost infinity variations of the inputs, temperature etc. so it is physically impossible to achieve 100 % test coverage. Perhaps this actually means 100% significant test coverage.
So are the inputs to the analog logic digital? Look at...
You handle separate clock domains by:
1) Assigning each clock domain a separate test clock pin.
2) During test generation force each clock to be pulsed in a separate test cycle. This will prevent you from having to mask cross clock domain captured values.
3) The scan stitching tool will add...
ATPGs generally work on designs that have the flip-flops connected into a scan chain. This allows you to load values into them before tests and see values that they capture after a test is applied. It converts a sequential test problem into a much simpler combinatorial problem because the tests...
ATPG patterns are used to ensure that the actual chips match the specification (netlist). That is to say they are applied by a tester to find chips with manufacturing defects.
You have to be careful not to have a bidirect conflict while testing your chip. A bidirect conflict occurs when you have the inputs driving opposite values on to the bus. It might also be a problem if they drive the same value. Depends on technology I think.
While scanning the bidir enables...
It is not clear what the problem is. My guess is that you don't really know or you english is insufficient for you to explain the problem you are seeing.
The following statement is incoherent:
Please try to explain this issue again.
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