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Recent content by comp_engineer

  1. C

    how to run MIPS multi-cycle processor on Xilinx Spartan 6 fpga

    no my top level is indeed hdl, i added a schematic by going to: project > new source (New SOurce Wizard dialog comes up) clicked on Schematic and named the file test clicked next, then clicked finish this added the schemtic to my project. but I don't know how to generate a schamtic based on...
  2. C

    how to run MIPS multi-cycle processor on Xilinx Spartan 6 fpga

    Thanks Sivamani, so I created a new project in ISE but I can't generate a programming file because its asking for a schemtic file, so I made a new schematic file but obviously its blank? is there a way I can generate a schematic based on my code? Or am I just going about this the wrong way...
  3. C

    how to run MIPS multi-cycle processor on Xilinx Spartan 6 fpga

    hello everyone So I wrote a Multi-Cycle Processor from scratch in Verilog HDL(I've tested it and it is indeed working fine), and I have purchased a Xilinx Spartan 6 FPGA (50mhz), and i'd like to implement or run this multi-cycle processor on this FPGA. In other words, I want to run my MC...
  4. C

    How to convert Single Cycle Processor to Pipelined Processor (no hazard unit)

    Hi everyone I'm working on converting a Single Cycle MIPS Processor I wrote in Verilog HDL into a Pipelined MIPS Processor. I'd just like some detailed guidance, programmatically speaking, about how I should go about this. I understand the main difference between the Single Cycle and the...
  5. C

    1 bit Rising-edge detector in verilog hdl

    I found the problem, it was in my next_state output logic. next_state should have been set to the current state /* State Assignments */ `define zero 2'b00 `define Edge 2'b01 //one `define one 2'b10 //terminate module MooreFSM(clk, reset, din, pe); input clk, reset, din; output reg pe...
  6. C

    1 bit Rising-edge detector in verilog hdl

    Okay, I tried to follow all of your suggestions the best I can here is what I came up with: /* Output only a function of the current state and the transitions between states are only functions of the current inputs */ /* State Assignments */ `define zero 2'b00 `define Edge 2'b01...
  7. C

    1 bit Rising-edge detector in verilog hdl

    I directly wrote this code from the drawing I made (which can be viewed in the original post), it follows exactly the drawing of the moore state diagram. I tried modeling my code from your suggestions but I kept getting synthesis errors, to be honest I still don't fully understand what you mean...
  8. C

    1 bit Rising-edge detector in verilog hdl

    You're suggestions were definitely helpful. Thanks:smile: Here is what I got, please don't hesitate to suggest improevments /* State Assignments */ `define zero 2'b00 `define Edge 2'b01 `define one 2'b10 module MooreFSM(clk, reset, din, pe); input clk, reset, din; output reg pe; reg...
  9. C

    1 bit Rising-edge detector in verilog hdl

    Thanks for the reply, I'm actually understanding better now but I'm still a little confused as how to translate your suggestions into code. Perhaps I don't fully understand your suggestions. You say that I need to make a 3rd state, what or how shall I make this third state? Since there is only 1...
  10. C

    1 bit Rising-edge detector in verilog hdl

    hi everyone I'm writing a Moore FSM for a rising-edge detector in Verilog HDL. I have essentially written the module but I am not sure as how to transition from the "edge" state to the one state. Please look at the diagram I drew that is attached to this post. Here are my design stipulations...
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