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Recent content by cnz

  1. C

    time scale selection in verilog

    Just FYI for rtl, 1ns/10ps for glv, 1ns/1ps
  2. C

    JTAG basics... Help me!

    Maybe JTV can help you! Please google "SiliconAid JTV", Hope to help you!
  3. C

    Need documents, materials about wafer probe test

    Re: about wafer probe test thanks. Yes, I know IEEE have a lots, But I have no access rights:cry:
  4. C

    DFT - are there any ways to improve fault coverage?

    DFT fault coverage 1) Try to remove all DRC vios firstly 2) Report all AU-fault, and check it
  5. C

    how to sync fast domain clock to slow domain clock domain

    fast clock to slow clock signal sync Maybe you can take slow clock as enable signal of fast clock, assume the two clock have the same phase
  6. C

    Need documents, materials about wafer probe test

    about wafer probe test Hi, all Now, I am one DFT Engineer, now engaged in wafer probe test, Would you please share the relarted docs with me if you have? thanks
  7. C

    DFT at speed testing question

    you should design a logic which can chop the clock pulse,chop out launch clock and capture clock.(broadside transition delay test) , Hope it can help you:)
  8. C

    how to control the keyboard within the dc_shell-t?

    ctrl+H can do it
  9. C

    What is Synopsys Module Complier for?

    Re: Module Complier In a word, MC can help you design datapath,such as +,-,*,÷. It can help you pipeline the datapath
  10. C

    I need a quick Synopsys Design Compiler tutorial!

    synopsys dc lab I rember someone have uploaded some dc workshop to this forum. it is a good start ponit.
  11. C

    about formal verification

    formal verification Hi all, usually,we use synopsys formality or cadence verplex-lec to do formal verification. Formal verification includes two type,one is equivalence checking,another is model checking. in its most common use,equivalence checking can do a check between RTL and...
  12. C

    set_input_delay in DC

    set_input_delay no clock alternative way is: Create a virtual clock that has only clock name and no clock source .
  13. C

    how to exceed the 2G file limit

    $fsdbautoswitchdumpfile in verilog yes. You can use the command "fsdbautoswitchdumpfile" to split huge file into many small file.
  14. C

    3d graphic ic start up document

    You can refer to Microsoft DirectX SDK help doc about DirectX3D.
  15. C

    Can't Start nclaunch of LDV 5.1 from The Linux Terminal

    libudm.so which shared object can not be found? Would you please describe it in detail?
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