DFT at speed testing question

[feel_on_on]

1. There is a PLL in my design. several PLL generated clock control my design,but also a external clock in my design.

2. Now I'm preparing to do at-speed scan testing. I insert a clock controller between PLL and my design. then I add a MUX with external clock and one PLL generated clock . When scan_mode = 1, PLL generated clock work for At-Speed test.

May not clearly I speak ,But I believe someone have done At-Speed testing can understand what i said .
please give a good advice.

 

[dft_guy]

Designing an at-speed clock controller is pretty involved. However, there's no question in your statements. You might try dftforum.com - there's more DFT experts over there.

 

[diag]

I am research at speed test now , i think we need PLL controller , to make sure all pll turn on during capture cycle . Pls correct me if i am wrong .

 

[santhosh007]

I am research at speed test now , i think we need PLL controller , to make sure all pll turn on during capture cycle . Pls correct me if i am wrong .

you should initialize your PLL in test setup.
you might be generating the at speed patterns single clock at a time. As soon as your pll is locked, you can tap those two capture pulses from pll by using clock control logic.

 

[cnz]

you should design a logic which can chop the clock pulse,chop out launch clock and capture clock.(broadside transition delay test) , Hope it can help you