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I find a question.
IN my vhdl file , I used file_open function and added" use STD.TEXTIO.all "to the vhd file.
SO, I think the prototype of file_open should in textio.vhd.
I opened the file in my modelsim path.
However, to my surprise, it doesn't contain file_open function !
what's the reason ?
Hi,
I am trying to debug VHDL using debussy(Red Hat OS).
As you know, debussy's nWave needs a *.fsdb file. But , I can't find the right way to generate *.fsdb file using Modelsim.
I searched the Internet and added
process
begin
fsdbDumpfile("counter.fsdb");
fsdbDumpvars(0...
There are two different expression
1.reg baud_rate=3;
wire [15:0] one_bit_clock_nums;
assign one_bit_clock_nums =2083/(2^baud_rate);
2.assign one_bit_clock_nums =2083/8;
In ModelSim,
the result are
1.2083
2.260
what's the reason?
BTW,Is division Synthesizable?
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