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Recent content by claint

  1. C

    Which Cadence tools support fully SystemVerilog ?

    systemverilog tools cadence There is no tools of Cadence can fullu support systemVerilog.
  2. C

    How to ensure a safe clock gating?

    Re: safe clock gating? You should set_clock_gating_check in STA
  3. C

    A question about digital module timing constraint!

    the hold value (0.4) is the new data available time after the posedge of clock. If this value is 0, then mim output delay is just the min path delay out of chip. so the constrained internal path delay inside chip is -min_delay. If the hold value is greater than zero, it requires that the data...
  4. C

    How are functions and tasks technology dependent?

    Re: Functions and Tasks No.
  5. C

    How to estimate chip power consume?

    Who can provide some papers or user guide of the powerthetre flow?
  6. C

    what EDA Tool can do hardware/software co-verification?

    Synopsys' System Studio is used to model HW/SW architecture to evaluate the performance of architecture, not used for co-verification.
  7. C

    How to make a complete plan to verify a mcu?

    Re: how to verify a mcu Hi,omara007, first Q: 2- Making sure that the testing programs do cover everything must be done thru profiling tools. These profiling (or reporting) tools should give you a complete automatic picture on the used programs without a need to go manually inside them. What...
  8. C

    muxed flip-flop scan chain insertion question

    muxed flip flop 3. a.You should use the following command to rst_b without set_test_hold command on rst_b set_signal_type -test_async_inverted rst_b b.You can leave the rst_b without constraint. i.e.,neither set_signal_type nor set_test_hold command is applied to rst_b, DC can recognize rst_b...
  9. C

    When to add IO buffers during flow?

    You choose IO type from the library of your vendor and instantiate IO in a module in RTL stage.
  10. C

    What tool are you using to insert jtag circuit??

    BSD compiler which is integrated in DC.
  11. C

    How about signed adder?

    16 bit signed adder 1.Use 2's complement all through the design,there is no need to convert to 1's complement. 2. If two data are both in [-1 1), and the number of bit is n, then use n+1 bit adder, there is no overflow. sum is in [-2 2), 3. n bit to n+1 bit cinversion: sign extended. 4. if you...
  12. C

    set_fix_hold ,what means?

    DC try to fix hold violations in the clock domain.
  13. C

    What is input delay and output delay?

    Yes,you should search in sold , you will be clear after reading dc related documents.
  14. C

    How to pipeline Loop Logic?

    Is your logic DSP alogorithm related? If it is (for example,IIR filter) ,use clustered look-ahead , scattered look ahead method to translate the prototype algorithm to architecture. Generally, loop logic is not easilly pipelined.
  15. C

    what's meaning about those in PT

    Hi, the clock pin of every register has different path delay from the source clock pin. launch latency is the clock path delay the lauched register which lauch data on the Q/Qbar pin.while the capture lantency is the clock path delay the captured register which capture data on the D pin. To...
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