How to ensure a safe clock gating?

[geegle]

I'm designing a clock controller, how could I ensure glitch-free?

 

[claint]

Re: safe clock gating?

You should set_clock_gating_check in STA

 

[skymusic]

Re: safe clock gating?

Use a latch, and AND gate to generate gated-clock. This gated-clock can be free from glitch.
-----------
D----- | LATCH | _____
| |_____| |
--o| |q | |
| |_______| | AND |------clk-out
clk|_______________ | |
|_____|

Added after 7 minutes:

At the same time, please run sta

 

[BlueSky68]

Re: safe clock gating?

I agree that An AND gate with a negative Latch is the most popular circuit available. However, you need to pay attention when you do STA. Also, you need to watch out how many flops each clock gating circuit could drive 1--> 8 or 1--> 16.

Be careful.

 

[funzero]

Re: safe clock gating?

Darren Jones, “ How to successfully use gated. clocking in an ASIC design,” SNUG Boston,. 2002.

Added after 21 seconds:

http://www.snug-universal.org/cgi-bin/search/search.cgi?Ottawa,+2003

 

[zhangpengyu]

safe clock gating?

use clock gating.