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needforspeed,
You got it, I must keep my PLL stable in different corners , different reference frequency, and the full range of integer N in feedback divider.
Yes, I have read many datasheets and found an external resister is usually employed to generate Ic.
Thanks.
Yes, the current Ic is generated by the charge pump, but I want to know where does Ic copy from? I mean how to generate the bias current for charge pump?
generate ic
Hi,
I want to know how to generate charge/discharge current Ic in a CPPLL?
Use a bandgap? I think it will take up a large size.
A simple supply-independent bias current can vary more than twice in worst case, and it may cause instability?
Any other solution?
Thanks in advance ^_^
cadence pll simulation
Hi,
When I simulate a PLL in Cadence spectre ADE, it runs too slow (about one day for a 20us tran simulation) and takes up a large space (up to 20GB).
So, how can I avoid this problem? If I use AMS or verilog-A, the result is OK? I mean the phase noise and jitter etc...
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