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Hi,
I have a pll which can bypass the pllout with input reference clock.
So when I force bypass=1, then the input reference clock is output to the pllout.
How to describe for DFT compiler this special connection and treat the reference clock as a scan clock ?
set_dft_signal -view existing_dft...
I ran tetramax atpg on my netlist with scan insertion.
This generates the patterns to exercise possible faults.
Now I ran
write_testbench -input xyz.spf -output xyz_tb
Supposedly this step creates the testbench and data input with expected output file
xyz_tb.v and xyz_tb.dat
and runs...
Hi,
I'm setting certain elements to NOT be scanned.
But looks like set_dft_configuration overrides this.
1) set_dft_configuration (acts like autofix)
Need someone to confirm.
set_scan_element false { module1 module2 }
set_dft_configuration -fix clock_enable
set_dft_configuration -fix reset...
Hi,
I'm a little confused by DFT compiler and usage.
I understand that the normal clock is defined as the ScanClock with existing_dft
but I'm adding a bypass MUX in RTL.
Seems like the clock used for scan chain insertion ALWAYS uses functional clk name. In this case : clk.
Seems like the...
Hi,
I have a custom block that needs special scan test pattern.
What are the tetramax commands to read in user created test patterns for a particular scan chain and run atpg to generate and report faults ?
Hi,
I have a dft setup where there are 8 blocks of logic to be scanned.
I was thinking of using
define_test_mode A0 -usage -scan -encoding {TEST[3] 0 TEST[2] 0 TEST[1] 0 TEST[0] 1}
. . .
and create the 8 test modes.
These 8 blocks will have one common scan input and one common scan output...
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