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clock domain crossing handshake
The solution for crossing clock domain is depended on what's to sync,
Double sync works on most of case; use the signal after double sync INPUT to working clock domain, and double sync the OUTPUT to output
clock domain.
But some case you will need to calculate...
synopsys db format
hi,
there is no easy way to convert db to lib directly,
one way to do that is under design or library compiler,
link the db and switch current design from cell to cell
to write out timing model as .lib.
Scripting will speed up this trail.
Nice flow by alway@smart.
Here is just some opion;
- check STA(static timing analysis) after delay calculation.
once get the SDF, using PrimeTime or whatever tools to check timing.
(most important ** MAKE SURE THERE IS NO TIMING LOOP in design)
- If timing is fine, try turn ON/OFF...
Verilog is more popular at bayarea.
VHDL is still welcom at Japan & Europe.
VHDL is more robust on synthesis; it won't give any surprise.
Verilog has more flexibility and is powerful on TestBench, like PLI ..
but, will need formal verification between RTL & netlist. And this
give EDA company...
Re: PowerCompile
It's embeded inside DC back from 2001 version.
But, it doesn't do a really good job.
What it really does is trying to find the register (flip-flop) can use
gated clock, and some datapath re-structure.
For next release; claimed by synopsys; they will have dual
library...
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