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Hi,
In order to simulate your IBIS file in HSPICE, then you need to create a hspice deck. The syntax of which is specified in the HSPICE user guide. Alternately you can even simulate it in cadence using the ibis2spice utility and simulating it in spectre. Or else you can even convert the IBIS...
Hi anand,
Drivers have high resistance in the saturation region. So in order to get a realistic resistance from IBIS models you should concentrate on the linear region of the pull-up and pull-down transistors. In the I-V table of IBIS file locate two points wherein the current-voltage are...
Hi icd,
IBIS models can be read by SI tools such as cadence allegro pcb. To use IBIS in spice simulators you need to first convert it to spice deck. You can use cadence ibis2spice for conversion.
Hi,
Recently we find too many advertising messages in forums like digital design. This is very irritating as we have to spend time segregating the real useful messages from these advertising messages. Can we get rid of these.
Regards
Chethan
Are you asking about the pin capacitance? If you are asking about pin capacitance of an IO pad, then it depends upon the pad type(ie., MFIO pads,IIC pads etc). Typically for 65nm it is around 2pf.
the command for simulating ur verilog test bench is same. both ncverilog and verilogxl have graphical interface. U need to invoke them in ur test bench. ur test bench shd contain all vectors for which u want to see if functionality is correct.
Re: m.s or mtech in vlsi
depends upon whether u want to work in India or US. If you want to work in US then dont think twice. Join for MS in any good US university if u can afford. But if u do an MTech in India u still have good opportunities for Jobs in India. But then going to onsite to US...
Hi,
most analog companies in India dont do the core analog design. its mostly a small IP blocks. average salary for an analog/rf designer with 10 years of exp can be anywhere from Rs 20L/annum to 30L/annum
If you want to do a generic timing analysis using some bench mark circuits then u can build a verilog test bench and simulate them. create a test bench using any standard verilog tools like ncverilog or verilogxl and simulate ur design.
Hi,
If your verilog code is a small one, then you can handwrite the schematic by reading the verilog file. But again there are no tools which can convert your verilog code to schematic.
Hi,
fast corner gives most optimistic results while slow corner gives most pessimistic results. Timing is closed on typical corner while even considering fast and slow because in practical environment situations it is the typical condition that the IC is in in most cases. Hence many setup/hold...
Hi,
You cannot get a verilog file from a schematic. No tools are soo intelligent. You can get a schematic netlist from a schmatic. That is a transistor/gate level description of your circuit.
regards
Chethan
Hi,
If you already have the verilog file ready, then
1) To compile verilog file, just use the command "verilog <File name>" if you have verilogXL else use the command "ncverilog <File name>" if you have ncverilog
2) To simulate the verilog file you need a test bench. It should contain all the...
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