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Recent content by Cesar0182

  1. C

    Error : "Cannot connect a VHDL scalar signal to Verilog vector port" in Modelsim

    gracias por la ayuda, acabo de resolver el error modificando la siguiente línea [CÓDIGO]rd_data_slv_f1 de señal : std_logic_vector(0 hasta 0); [/CÓDIGO] 1634759045 thanks for the help, I just solved the error by modifying the following line. signal rd_data_slv_f1 ...
  2. C

    Error : "Cannot connect a VHDL scalar signal to Verilog vector port" in Modelsim

    Greetings, let you know that I have found an example of an asynchronous fifo in verilog and I have implemented it to my vhdl project in Vivado 20192.2 but I am having problems trying to simulate it in Modelsim SE 10.5. I am getting the following error from the image. Could someone help me with...
  3. C

    How to modify delay cycles to enable reading in fifo generator?

    thanks for answering @dpaul, sorry I meant ISE 14.5. Tell you that I don't have the read_count and write_count counters enabled, how could I use them to speed up the empty signal?
  4. C

    How to modify delay cycles to enable reading in fifo generator?

    Greetings, tell you that I am implementing a SPI design in ISE 17.5 using an asynchronous fifo. The problem I am having is that there is a delay of 5 to 6 read clock cycles (rd_clk = 25 MHz) after writing the first data (wr_clk = 100 Mhz) so that the data written in the fifo is enabled to be...
  5. C

    Where can I get information to implement a PLL programmable clock in virtex 5?

    Greetings ... comment that I need to implement a programmable clock based on a PLL with ISE 14.5 for the Virtex 5 family (similar to the following example https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf) but I cannot find information about the...
  6. C

    Simulation code for project with Aurora 8b10b in Vivado.

    Greetings, I comment that a couple of weeks ago I have migrated a project made in ISE 14.5 to Vivado 2019.2. At the moment I have managed to update all the IPs and I have also prepared it. But at the time of the simulation I have seen that the Aurora 8b10b kernel (updated) is not working in the...
  7. C

    Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

    thanks for the help @niciki , i was finally able to solve my problem.
  8. C

    Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

    I attach the source files and the compressed IP I am using. @niciki I tell you that I have changed to "include shared logic in core" but I am having the same error.
  9. C

    Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

    @niciki these are all the configuration options
  10. C

    Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

    I have not really synthesized the project, the errors I get are when I elaborate it.
  11. C

    Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

    thanks for your answer @TrickyDicky and @niciki , I just implemented logic to adapt tkeep from 3 bit (Aurora 8B10B v5.3) to 8 bit (Aurora 8B10B v11.1), but I am getting the following errors while synthesizing. Could you explain to me why this happens? I have been able to verify that those...
  12. C

    Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

    Greetings, tell you that a couple of days ago I am migrating a project for a Virtex-5 made in ISE 14.5 to Kintex Ultrascale in Vivado 2019.2. At the moment I have managed to update and adapt almost all the ip cores with the exception of Aurora 8B10B since I cannot generate the same size of the...
  13. C

    How to add the ip core of a FIFO using tcl console in ISE 14.5?

    I did what you recommended, but I still see the GUI still using only the same command. When creating an ip core in Vivado, it is true that the .xci file is generated and loaded with the following command. read_ip ../../../build/coregen/l1_coregen_tx_data_fifo/l1_coregen_wbus_client_fifo.xci...
  14. C

    How to add the ip core of a FIFO using tcl console in ISE 14.5?

    if you are right, the code I am using to load the ip cores are the same ones used by the ISE GUI. I thought this would work.
  15. C

    How to add the ip core of a FIFO using tcl console in ISE 14.5?

    Greetings ... can someone explain to me how I can load the ip core of a FIFO 9.3 with the tcl console of ISE 14.5? I have been trying to edit a l1_top.prj file where all the source code and ip cores are loaded for my project. But I am having trouble adding the ip core of a FIFO in the following...
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