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Thanks for all replies.
I think I should explain the situation in more detail, namely, why I need reference voltages from 0.807 to 0.969V with 16 taps @ 0.0108V steps. Perhaps by explaining the big picture, it might be more helpful.
It is because I am using it in non-inverting amplifier...
This is for CMOS IC design.
Although there are 17 references in total, only 0.75V and 1 of 16 of the references are ever used and the intent is to select it via analog mux. The 0.75V and 1 of16 taps drives the inputs of 2 OTAs which are FETs so no current load whatsoever.
Scaling all the...
So then if I had to choose between the two schemes, (b) 128 unit resistor ladder is better, in your opinion.
Not quite sure I understand this part.
If I understand correctly, in order to get 750m, 807m and 969m taps with integer segments, I'd need 1500 resistors in series. Not sure that is...
I am needing to generate somewhat precise voltage references. I have access to 1.5V.
I need the following references:
0.75V
0.807V to 0.969V in 0.0108V steps (so 16 references in total)
I am considering these two options using poly resistors:
----------------------------------------
1) From...
Hello:
I am trying to create a voltage controlled resistor in Verilog-A with the following behavior:
if V(res) <= 0.3 resistance = 5k;
if V(res) >0.3 && V(res) < 0.5 resistance = 2k;
if V(res) >= 0.5 resistance = 10k;
I haven't been able to get this to work.
I can't get the second part to...
The voltage doubler uses charge pump action to drive the Vo from Vdd to 2*Vdd. The pumping action is driven by the oscillator. When the oscillator stops running, Vo will slowly fall due to the Rload. To regulate Vo, we use the bang-bang feedback to turn the oscillator ON when below Vref and OFF...
Thanks for all replies.
After thinking about the easiest way to do this the best I can come up with is:
Use the BGR to generate the PTAT voltage, select points inside "inside" the R2 resistor to select the slope. Of course this selects both the slope and the intercept at the same time!
Then...
I am designing the following circuit:
The voltage doubler is just the standard crossed couple voltage doubler.
The oscillator is just a ring oscillator with a NAND-gate to provide enable functionality.
I used a behavioral model for the schmitt trigger comparator.
I am able to get it to work...
I am trying to design a CTAT voltage generator such that:
Vout = mx + b
where I can control both m and b separately.
The closest I can come up with is using the CTAT voltage of a bandgap reference circuit.
If R2 is actually several transistors in series, then I can select different taps...
Thanks for your reply and good point about (b) having larger output swing. But if the output swing with (a) is sufficient, then it seems there is no reason to use (b), right?
As for supporting larger Rout load, you could just as easily use (a) but with larger sized FETs, instead of using (b)...
In the project I am working on there are various 1 or 2 stage opamps.
(a) Simple Opamp (b) Current Mirror Opamp
I am seeing the following two types of first stage topologies.
But it isn't clear why (b) was chosen instead of (a) in certain sub-cells. I literally...
I am very new to Frac-N PLL design. This is where you can get Fvco=(N+K/M)Fref, where N, K and M are integers and K < M (and M is 2^m).
The simplest way to implement Frac-N is using a first order delta-sigma modulator (DSM). But it has bad performance due to large spurs. You get a repeating...
I'm not that familiar with multi-bit SD modulator. Is that just several 1-bit SDM in parallel?
In any case, for Frac-N modulation, they definitely call it second or higher order sigma delta modulation. Here is a TI document on this.
https://www.ti.com/lit/an/snaa062a/snaa062a.pdf
Here is their...
I've been studying Fractional-N PLL design and learned that you can implement it using a first order DAC. Frac-N PLLs can divide by N+A/B.
You can do this by dividing by N for B-A reference clk cycles and N+1 for A cycles. The average Fvco/Fref is then (N+A/B)
The first order DAC is as follows...
Okay I've had time to put together a version of this circuit using LTSpice.
If you fix the vctrl (the PMOS active load gate voltage), Fvco increases with Itail initially. I believe in this region the PMOS active loads are in triode.
But then I think the PMOS active loads start going into...
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