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Recent content by carrot

  1. C

    how to verify 70% and 30% clock cycle

    I want to test this in simulation. Digital solution.
  2. C

    how to verify 70% and 30% clock cycle

    Hi - Can anyone help me in telling, How do verify 70% on and 30% clock cycle ? Thanks, Carrot
  3. C

    NVMe Protocol Command

    Hi - Anyone aware of the purpose of NVMe Protocol flush command ? Thanks, Carrot
  4. C

    What are the types of New & Virtual in SV ?

    Hi All, I heard a couple of questions on system verilog very recently...... 1. What are the types of new ? ( the hint given was, there are 4 types of new ) Is there really 4 types of new in system verilog? 2. What are the different types of Virtual ? I'am really unaware of these 4...
  5. C

    Need Code for 0 to 1 Transition

    Need Synchrounous clock, with any other simple method. Thanks
  6. C

    Need Code for 0 to 1 Transition

    Hi , When input is transitioning from 0 to 1, output should be asserted for 1 cycle (in same cycle) with synchronous clock. how will the verilog code look like? Thanks, Carrot
  7. C

    Tasks and Functions - Performance

    Hi, Which is better in terms of performance - Tasks or functions? I have observed - Many of them use Functions rather than Tasks? How is it useful in terms of Performance? Thanks
  8. C

    Doubt in Functionality of DDR3

    Hi, Can anyone help me in understanding the below two sentences especially the second sentence: The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a...
  9. C

    difference between compile time, run time and elaboration time

    Cyboman, During Elaboration phase, my understanding is the compiled code (took place during compilation phase) will be converted to machine understandable format. Carrot
  10. C

    difference between compile time, run time and elaboration time

    The squence is : Compilation Phase -> Elaboration Phase -> Run (Simulation)
  11. C

    AMBA AXI Interface questions

    Definitely you can initiate the second address or data before the response for the first transaction is sent from the slave. It is purely dependent on the number of outstanding transactions that is supported - Generally it should be configurable.
  12. C

    help 4 system verilog

    Hi, If you are interested to learn system verilog, then you can go through the below site which would be useful. WWW.TESTBENCH.IN WELCOME TO WORLD OF ASIC
  13. C

    Static and Automatic Variables

    Hi, Can anyone let me know the difference between Static and Automatic Variables with an example? Thanks in Advance, Carrot
  14. C

    vlsi jobs in chennai ?

    Hello sree205, You can also add Cisco to that list - They are not full fledged but do have a small group of people. Cheers, Carrot
  15. C

    What are the advantages of AHB over AXI bus protocol ?

    Re: AHB V AXI In AXI - once you initiate a transaction, unless you get a response back, you cannot initiate next transaction. In AHB - hope split-retry mechanism is available, with which the next transaction can be initiated, without responding for the first transaction
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