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Hi,
Can anyone tell me how to write testbench for clock with offset.
Here is my test bench
process
begin
clk1 <= '1'; wait for 10ns;
clk1 <= '0';wait for 10ns;
end process;
process
begin
clk2 <= '0';(other signal);wait for 5ns;
clk2 <= '1';(others signal);wait for 10ns;
clk2 <=...
I build my own fpga spartan 3 test board based on spartan 3E starter kit design.
When i power on my board, ISE impact can't detect my xilinx ic. How i can make sure my xilinx ic is in good condition.
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