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Recent content by brunokasimin

  1. B

    What is actually startup code??

    Re: startup code Do you refer main() as the one fromC program?
  2. B

    What is actually startup code??

    startup code What is actually startup code?? From what i knew, Startup code is executed immediately upon reset of the target system.I have been looking for the easy explanation in google but could not find the simple explanation..Can somebody explain me in easy detail??
  3. B

    loading of Memory Initialization File in FpgAdv

    hello, I'm having a problem with the loading of MIF files. How to include the .MIF file actually? I just added the .MIF file in my design but it was not found. the error is as follows: Warning: Critical Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File...
  4. B

    warning message in precision

    hello, After synthesization, i got the following warning: # Warning: [237]: Found black-box: zpu_leds_blink.lpm_ram_dq_RTLC_LONGENT0; "Z:/hds_project/HDS/test/zpu_leds_blink/hdl/prom.vhd", line 47:. what is actually black box?
  5. B

    looking for both quartus and FpgAdv expert(urgent)

    hello, is anyone out there expert on both of these topics?
  6. B

    general purpose input output

    hello, can we consider that general I/O is a peripheral??
  7. B

    guide me how to write a report

    can you give me the links..will give your points
  8. B

    guide me how to write a report

    hello all, i have a student research project with title of 'implementation of soft-core processor on fpga'..i've a created a few vhdl modules to connect the processor to the port of LED...can somebody give me example or guide me to write the report??
  9. B

    looking for both verilog and vhdl expert

    i will give 30 points if it is fully translated/almost
  10. B

    looking for both verilog and vhdl expert

    hello, thx for ready to help me. i learned only VHDL codes and i don't understand verilog. I need to translate few verilog modules as soon as possible. To learn Verilog is also time consuming, thats why i need someone who can help me.. Here is the first code: `define TECH_ALTERA module wb_bram...
  11. B

    looking for both verilog and vhdl expert

    hello, Is anyone out there expert in both verilog and vhdl?? i really need help!! thx in adv regard, bruno
  12. B

    is always@(posedge clk) similar to rising_edge(clk)??

    Re: always @(posedge clk) hello, for example, here is a verilog code: always @(posedge clk) begin err <= 0; if (ce && (addr[0] || addr[1])) err <= 1; end so, i can write a vhdl code here like this: elsif rising_edge(clk) then err <= '0'; if(ce && (addr(0) or addr(1))) then...
  13. B

    is always@(posedge clk) similar to rising_edge(clk)??

    always @(posedge clk) hello, is always@(posedge clk) similar to rising_edge(clk)?? thx
  14. B

    verilog to vhdl translation 1

    verilog to vhdl translator hello, here is my small verilog code: sel_ram <= op and (wb_i_adr[31:30] == 2'b11); sel_rom <= op and (wb_i_adr[31:30] == 2'b00); sel_io <= op and (wb_i_adr[31:30] == 2'b01); and i translated into vhdl: if wb_i_adr(31 downto 0)= "11" then sel_ram <= op and "11"...
  15. B

    Help me convert a Verilog code to VHDL

    igpio hello, i have a difficulty to convert the following verilog programme to vhdl. i dont understand verilog at all..can somebody convert it to me??? below is the files module gpio ( input clk, input rst, input ce, input we, output reg ack, input addr, input [31:0]...
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