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Help me convert a Verilog code to VHDL

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brunokasimin

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igpio

hello,

i have a difficulty to convert the following verilog programme to vhdl. i dont understand verilog at all..can somebody convert it to me??? below is the files

module gpio (
input clk,
input rst,
input ce,
input we,
output reg ack,
input addr,
input [31:0] dati,
output reg [31:0] dato,
inout [31:0] GPIO,
input [31:0] GPIO_I
);

parameter INPUTONLY = 32'h00000000;

reg [31:0] dat_q;
reg [31:0] tris_q;
wire [31:0] IGPIO;
genvar tr;

generate
for (tr=0; tr<32; tr=tr+1)
begin: gpio_buf
if ( INPUTONLY[tr] == 0) begin
/*
IOBUF gpioiob (
.I( dat_q[tr] ),
.O( IGPIO[tr] ),
.IO( GPIO[tr] ),
.T ( tris_q[tr] )
);
*/
assign GPIO[tr] = tris_q[tr] ? 1'bZ: dat_q[tr];
assign IGPIO[tr] = GPIO[tr];
end else begin
/* IBUF gpioiob_o (
.I ( GPIO_I[tr] ),
.O ( IGPIO[tr] )
);*/
assign IGPIO[tr] = GPIO_I[tr];
assign GPIO[tr] = 1'bZ;
// assign
//assign IGPIO[tr] = 1'b0;
end
end
endgenerate

always @(posedge clk or posedge rst)
begin
if (rst) begin
tris_q <= 32'hFFFFFFFF;
dat_q <= 32'h00000000;
ack <= 0;
end else begin
ack <= 0;
if (!ack && ce) begin
if (addr) begin
tris_q <= dati;
end else begin
if (we)
dat_q <= dati;
else begin
dato <= IGPIO;
end
end
ack <= 1;
end
end
end

endmodule






thx
 

gpio & vhdl

probably u can donate some points to get the work done :D

Added after 4 minutes:

u can try this :
**broken link removed**
 

verilog iobuf

You can use:
[1] X-HDL
[2] SynaptiCAD v2v
 

v2v synapticad

X-HDL is very helpful. you can try it.
 

gpio vhdl

HI,

u can try altera quartus ii to convert ur code from vhdl to verilog ot it can convert vhdl to schmetic and schmetic to verilog.

it may help u.

Thanks..

HAK..
 

Re: verilog to vhdl

u can use xhdl tool , itis verv effective but it may ase some errors but at least it will make u understand the code.......
 

verilog to vhdl

there is a vhdl to verilog tool too ?
 

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