looking for both verilog and vhdl expert

[brunokasimin]

hello,

Is anyone out there expert in both verilog and vhdl?? i really need help!!
thx in adv

regard,
bruno

 

[Zerox100]

What is your problem? may be I can help you?

 

[brunokasimin]

hello,
thx for ready to help me. i learned only VHDL codes and i don't understand verilog. I need to translate few verilog modules as soon as possible. To learn Verilog is also time consuming, thats why i need someone who can help me..

Here is the first code:

`define TECH_ALTERA
module wb_bram (
clk,
rst,
ce,
we,
addr,
dati,
dato,
ack
);

parameter ASIZE = 12;

reg [31:0] memory [ASIZE-3:0];
input [ASIZE-1:0] addr;
input clk;
input rst;
input ce;
input we;
input [31:0] dati;
output [31:0] dato;
output reg ack;

wire ceint;

assign ceint = ce && ~ack;

always @(posedge clk)
begin
ack <= 0;
if (ceint) begin
ack <= 1;
end
end


`ifdef TECH_ALTERA

wire wr;
assign wr = ce & we;

initial $display("Using Altera LPM.");

lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(dati),
.we(wr),
.q(dato)
);

defparam lpm_ram_dq_component.lpm_width = 32,
lpm_ram_dq_component.lpm_widthad = ASIZE,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "REGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
`endif // TECH_ALTERA

endmodule

 

[brunokasimin]

i will give 30 points if it is fully translated/almost