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We can characterize Nmos, Pmos transistor of a standard cell in Typical (T), Slow (S) and Fast (F) modes. So, when we say TT mode.. Nmos transistor is characterized in Typical (T), Pmos transistor is characterized in Typical (T) mode.
In order to maintain the duty cycle, you need to ensure that both rise and fall edges have similar transitions (if possible same transitions). And as narfnarf mentioned.. "instead of of using buffers/inverters with the same rise and fall time. CTS tries to balance the load and driver.."
Also...
I guess you are referring Milkyway database that is 'proprietary' to Synopsys tools. Synopsys APR tools (like IC Compiler) work on milkyway database that is created for all standard cells/RAMs. This would be generated by library team for each technology node.. not sure what you mean when you...
We have taped-out with few (2-3ps) setup and hold slack but the violations are in non-critical corners (like Slow-Slow setup mode or Slow-Slow hold mode with worst-RCs etc.). Also at times when the violations are in Scan mode.
But we need to ensure we have clean timing in the 'all critical'...
Firstly, as PNR tools deal Metal layers, any violations seen in Base Layers (like Poly, OD etc.) will not be seen by PNR tools.
Secondly, for Metal layers there could be violations like Manufacturing grid (off-grid) violations, Metal Density, Via Enclosure etc. will not be seen by PNR tools.
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