multi scenario questions

[eeStud]

Hi all,
I have some question regarding multi scenario:
i understand why we need different scenarios, but i have problem understanding the results.
suppose i have 3 different scenarios, each scenario has library cells, derate factor etc. and i am running the flow in IC COMPILER for all three of them, what is the result?
i am not getting 3 different designs, so how it manifests that i set 3 scenarios?

thanks, and i hope my question was clear.

 

[phoenixpavan]

Hi erezb,

a scenario in ICC is defined as corner+mode..so when u define a scenario for analysis you are considering all the possible conditions in which a chip may work and analyze for it for more accurate reports

cheers,

 

[eeStud]

Hi,
yes, i understand it,
i understand it effect the reports in prime time,
but what i dont understand is how it effects the flow step (placement, route, cts ...)

 

[damonzhao]

you means you can get 3 different report if you use 3 scenario?
yes, you can use the scenario separately, then you will get 3 reports. and you diff them to find what the differences

 

[birdy123]

Hi,

looks like you have some confusion regarding the use of the scenario. As pavan mentioned that its combination of Corner +mode, so first you have to understand what exactly it means...

Its very difficult for me right now to capture all the points here.. ( I will do sometime in the weekend.. if you require).. but right now just in short ..

• In general, there are lot of PVT corners and 5 Parasitic corners in a particular design.
o Process- TT, SS and FF (mostly used- not FS and SF)
o Voltage- as per the design requirement. For Multi-voltage, it will increase as per the voltage domain.
o Temperature – in general -40deg, 0deg, 25deg and 125deg.
o Parasitic Corners – Rcworst, Rworst, RCbest, Cbest and Typical.
• For lower technology, these number (count of corners) are increases because it’s very difficult to find out the single worst and best corner for the design. Means the extreme conditions on which chip suppose to evaluate, can’t be covered by single worst and best corner . There are lot of reasons for that.

So now if I will talk about the library data or flow regarding these corners.. so you will find different libraries for each corner (in general).

So there are couple of change sin the flow...
1) input libraries will change ( means all the referance libraries)
2) if you have any corner specific constraint .. then you have to add that.
3) in ICC or in any other tool - there are few specific setting with respect to sceniorio. Like if you delaing with max library then in few of commands you have to add switch - case max .. or in case of min -case min or similar to that.
4) during timing analysis-- may be you wanted to do OCV (onchip variation) analysis .. or BC (best case) alone or worst case alone or may be BC/WC together.. then there are different switches in the commands.
5) since you are using different libraries .. e.g fast and slow. so in the flow during fixing a violation you cann't use same methodology every time. you have to change your flow a bit in terms of fixing a violation.

So similar to that there are lot of changes in flow but those are not like .. you can do DRC checking first and PNR later. hehhe..

May be you got my point. If you need any other detail .. let meknow .. I will try to capture those in detail next time.

 

[pavanks]

Hi,

looks like you have some confusion regarding the use of the scenario. As pavan mentioned that its combination of Corner +mode, so first you have to understand what exactly it means...

Its very difficult for me right now to capture all the points here.. ( I will do sometime in the weekend.. if you require).. but right now just in short ..

• In general, there are lot of PVT corners and 5 Parasitic corners in a particular design.
o Process- TT, SS and FF (mostly used- not FS and SF)
o Voltage- as per the design requirement. For Multi-voltage, it will increase as per the voltage domain.
o Temperature – in general -40deg, 0deg, 25deg and 125deg.
o Parasitic Corners – Rcworst, Rworst, RCbest, Cbest and Typical.
• For lower technology, these number (count of corners) are increases because it’s very difficult to find out the single worst and best corner for the design. Means the extreme conditions on which chip suppose to evaluate, can’t be covered by single worst and best corner . There are lot of reasons for that.

So now if I will talk about the library data or flow regarding these corners.. so you will find different libraries for each corner (in general).

So there are couple of change sin the flow...
1) input libraries will change ( means all the referance libraries)
2) if you have any corner specific constraint .. then you have to add that.
3) in ICC or in any other tool - there are few specific setting with respect to sceniorio. Like if you delaing with max library then in few of commands you have to add switch - case max .. or in case of min -case min or similar to that.
4) during timing analysis-- may be you wanted to do OCV (onchip variation) analysis .. or BC (best case) alone or worst case alone or may be BC/WC together.. then there are different switches in the commands.
5) since you are using different libraries .. e.g fast and slow. so in the flow during fixing a violation you cann't use same methodology every time. you have to change your flow a bit in terms of fixing a violation.

So similar to that there are lot of changes in flow but those are not like .. you can do DRC checking first and PNR later. hehhe..

May be you got my point. If you need any other detail .. let meknow .. I will try to capture those in detail next time.

Please provide more information here as you have told whenever u get time

 

[huckle]

Process- TT, SS and FF (mostly used- not FS and SF)

Anyone please expand these abbreviations TT, SS and FF ? Thanks

 

[brs2k4]

Anyone please expand these abbreviations TT, SS and FF ? Thanks

We can characterize Nmos, Pmos transistor of a standard cell in Typical (T), Slow (S) and Fast (F) modes. So, when we say TT mode.. Nmos transistor is characterized in Typical (T), Pmos transistor is characterized in Typical (T) mode.

 

[birdy123]

Hi Pavan,

I will provide more infomration soon.. But it will be good if you ask specific question. Because this topic is so vast that its difficult to provide every thing here in one shot.